• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• Journal of the Korean Society of Safety
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• v.33 no.5
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• pp.120-126
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• 2018

The traffic accident types are largely classified into vehicle to vehicle accident, vehicle-to-person accident and single-vehicle. Especially, the single-vehicle accident types are severe when the vehicle crashed into road facilities such as bridge, piers, utility poles. The severity of single-vehicle accidents are ten times higher than that of all other accidents types. It is needed to consider to reduce accident severity. This study was conducted to develop crash worthy safety design facility to ensure the vehicle occupant safety. The simulation and the crash tests were conducted for assessment of the safety performance to check the criteria of CC2(Crash Cushion 2) level. THIV(Theoretical Head Impact Velocity) and PHD(Post-impact Head Deceleration) were used to assess occupant impact severity for crashes. The non-redirection collision test conditions for 900 kg and 1,300 kg-head on crash tests, 900 kg-1/4 offset crash tests, 1,300 kg-head on crash test with $15^{\circ}$angle were conducted. The simulation and experiment test result showed that THIV values were below 44 km/h criterion, PHD values were below the 20G. The development non-redirective crash cushion is expected to be used for the fixed object such as bridge piers for assuring occupant safety.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.282-290
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• 2006

In this paper, we propose an enhanced Timing Estimator algorithm for 2.45GHz LR-WPAN receiver. Because an expensive and highly efficient oscillator can't be used for low-cost implementation, a Timing Estimator algorithm having stable operation in the channel environment with center frequency tolerance of 80 ppm is required. To enhance the robustness to frequency offset and the stability of receiver performance, multiple delay differential filter is adopted. By utilizing the characteristic that the correlation result between the output signal of Multiple delay differential filter and reference signal is restricted on the In-phase part of the correlator output, a coherent detection scheme instead of the typical noncoherent one is adopted for Timing Estimator. The application of the coherent detection scheme is suitable for LR-WPAN receiver aimed at low-cost, low-power, and low-complexity, since it can remove performance degradation due to squaring loss of I/Q squaring operation and decrease implementation complexity. Computer simulation results show that the proposed algorithm achieved performance improvement compared with the differential detection-based noncoherent scheme by 2dB in average.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.2
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• pp.85-89
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• 2011

In this paper, a novel Class-E power amplifier using metamaterials has been realized with one RF LDMOS diffusion metal-oxide-semiconductor field effect transistor. The CRLH structure can lead to metamaterial transmission line with the Class-E power amplifier tuning capability. The CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Also, the proposed power amplifier has been realized by using the CRLH structure in the output matching network for better efficiency. Operating frequencies are chosen at 13.56 MHz in this work. The measured results show that the output power of 39.83 dBm and the gain of 11.83dB was obtained. At this point, we have obtained the power-added efficiency (PAE) of 73 % at operation frequency.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.2
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• pp.51-59
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• 2010

In this paper, we propose an inverted type asymmetric Doherty amplifier with optimized efficiency characteristic in wanted output power back-off (OPBO) range according to peak to average power ratio of input signal In order to obtain optimized efficiency of the asymmetric Doherty amplifier in wanted OPBO, peak power ratio between main amplifier and peaking amplifier was determined and then impedance of 90 degrees impedance transformer was obtained by peak power ratio. The offset line length and peak dividing ratio of the asymmetric Doherty amplifier were also calculated. From the measurement results, the proposed amplifier has achieved 40 % drain efficiency and -35 dBc adjacent channel leakage ratio at the average output power of 48.7 dBm for CDMA 2000 1x 3-FA test signal.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.46-52
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• 2009

In this paper, the timing estimator based on the principle of the best linear unbiased estimator (BLUE) is proposed in OFDMA uplink systems. The proposed timing estimator exploits the phase information of the differential correlation between adjacent subcarriers. The differential correlation can extract the information about timing offset and mitigate the distortion of the signal caused by the frequency selectivity of channel. Compared with conventional methods, the proposed estimator shows more accurate capability in estimation. In addition, the estimator is hardly affected by the distortion caused by the frequency selectivity of channel. Simulation results confirm that the proposed estimator shows a small error mean and a relatively small error variance. In addition, the performance of the estimator is evaluated by means of SNR loss. It is shown by simulations that the SNR loss of the proposed estimator by estimation errors is less than 0.4 dB for the SNR values between 0 and 20 dB. This might indicate that the proposed estimator is suitable for the timing synchronization of multiple users in OFDMA uplink systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Structural Engineering and Mechanics
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• v.46 no.2
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• pp.213-229
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• 2013

Although performance based assessment procedures are mainly developed for reinforced concrete and steel buildings, URM (Unreinforced Masonry) buildings occupy significant portion of buildings in earthquake prone areas of the world as well as in IRAN. Variability of material properties, non-engineered nature of the construction and difficulties in structural analysis of masonry walls make analysis of URM buildings challenging. Despite sophisticated finite element models satisfy the modeling requirements, extensive experimental data for definition of material behavior and high computational resources are needed. Recently, nonlinear equivalent frame models which are developed assigning lumped plastic hinges to isotropic and homogenous equivalent frame elements are used for nonlinear modeling of URM buildings. The equivalent frame models are not novel for the analysis of masonry structures, but the actual potentialities have not yet been completely studied, particularly for non-linear applications. In the present paper an effective tool for the non-linear static analysis of 2D masonry walls is presented. The work presented in this study is about performance assessment of unreinforced brick masonry buildings through nonlinear equivalent frame modeling technique. Reliability of the proposed models is tested with a reversed cyclic experiment conducted on a full scale, two-story URM building at the University of Pavia. The pushover curves were found to provide good agreement with the experimental backbone curves. Furthermore, the results of analysis show that EFM (Equivalent Frame Model) with Dolce RO (rigid offset zone) and shell element have good agreement with finite element software and experimental results.