• Title/Summary/Keyword: 2D Offset

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dB-Linear CMOS Variable Gain Amplifier for GPS Receiver (dB-선형적 특성을 가진 GPS 수신기를 위한 CMOS 가변 이득 증폭기)

  • Jo, Jun-Gi;Yoo, Chang-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.7
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    • pp.23-29
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    • 2011
  • A dB-linearity improved variable gain amplifier (VGA) for GPS receiver is presented. The Proposed dB-linear current generator has improved dB-linearity error of ${\pm}0.15$dB. The VGA for GPS is designed using proposed dB-linear current generator and composed of 3 stage amplifiers. The IF frequency is assumed as 4MHz and the linearity requirement of the VGA for GPS receiver is defined as 24dBm of IIP3 using cascaded IIP3 equation and the VGA satisfies 24dBm when minimum gain mode. The DC-offset voltage is eliminated using DC-offset cancelation loop. The gain range is from -8dB to 52dB and the dB-linearity error satisfies ${\pm}0.2$dB. The 3-dB frequency has range of 35MHz~106MHz for the gain range. The VGA is designed using 0.18${\mu}m$ CMOS process. The power consumption is 3mW with 1.8V supply voltage.

A Design of Predistortion Linearizer using 2nd Low Frequency Intermodulation Signal Injection (2차 저주파 혼변조 신호 주입을 이용한 전치 왜곡 선형 화기 설계)

  • Lee, Hyo-A;Lee, Chul-Whan;Jeong, Yong-Chae;Kim, Young;Kim, Chul-Dong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.9
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    • pp.967-973
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    • 2003
  • This paper presents a new predistortion method which injects the 2nd low-frequency intermodulation signal of RF signals into the input bias line of the amplifier. New 2nd intermodulation signal extraction circuit is also proposed. We have shown that this method can suppress the 3rd IM apparently and sometimes do the 5th IM, through mathematical analysis, then confirmed it with simulation and verified it on the desk test. When the input signal CDMA IS-95 lFA is applied, measured ACPR improvements are 25 dBc, 22.5 dBc, and 6 dBc at 0.885 MHz, l.25 MHz and 2.25 MHz offset respectively. Also, when applying the CDMA IS-95 3FA, the measured ACPR improvement is 20 dBc at 0.885 MHz offset.

Design of Ku-band Low Phase Noise Oscillator Using DSRR Structure Resonator based on Metamaterial (메타구조 기반의 DSRR 구조 공진기를 이용한 Ku 대역 저 위상잡음 발진기)

  • Yoon, Nanae;Seo, Chulhun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.2
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    • pp.19-22
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    • 2014
  • In this paper, Ku-band low phase noise oscillator using DSRR structure resonator based on metamaterial was proposed. To improve the phase noise of the oscillator, the proposed resonator consist of a DSRR strcuture based on metamaterial. The proposed resonator have a characteristic of $S_{11}$ is -0.25 dB, and $S_{21}$ in -44.59 dB at 14.67 GHz, respectively. At 14.67 GHz, the proposed Ku-band low phased oscillator achieves a output power of 2.03 dBm, $2^{nd}$ harmonic of -36.04 dBc, and phase noise of -130.63 dBc at the 100 kHz offset, respectively.

Link Scheduling Method Based on CAZAC Sequence for Device-to-Device Communication (D2D 통신 시스템을 위한 CAZAC 시퀀스 기반 링크 스케줄링 기법)

  • Kang, Wipil;Hwang, Won-Jun;Choi, Hyung-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.4
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    • pp.325-336
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    • 2013
  • FlashLinQ, one of the typical D2D communication systems developed by Qualcomm, considers a single-tone communication based distributed channel-aware link scheduling method to realize the link scheduling process with low control overheads. However, considering the frequency selective fading effect of practical multi-path channel, the single-tone based SIR estimation causes a critical scheduling error problem because the received single-tone signal has quite different channel gain at each sub-carrier location. In order to overcome this problem, we propose a novel link scheduling method based on CAZAC (Constant Amplitude Zero Auto-Correlation) sequence for D2D communication system. In the proposed method, each link has a unique offset value set for the generation of CAZAC sequences. CAZAC sequences with the cyclic offsets are transmitted using multiple sub-blocks in the entire bandwidth, and then each device can obtain nearly full-band SIR using a good cyclic cross-correlation property of CAZAC sequence.

A Semi-MMIC Hair-pin Resonator Oscillator for K-Band Application (K-Band용 SEmi-MMIC Hair-pin 공진발진기)

  • 이현태
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.9B
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    • pp.1635-1640
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    • 2000
  • In this paper, a 18 GHz oscillator is designed with the push-push method an fabricated by semi-MMIC process, in which the second harmonic is the main output signal with the suppressed fundamental mode. In semi-MMIC process, passive components with microstrip transmission line are implemented using MMIC process on semi-insulating GaAs substrate. Then, chip types of P-HEMT, resistors, and capacitors are connected through Au wire-bonding. Also, the ground plane is inserted around the circuit and connected each other with the back-side of substrate through Au wire-bonding instead of via-hole. The semi-MMIC push-push oscillator shows the output powder of -10.5 dBm, the fundamental frequency suppression of -17.3 dBc/Hz, and the phase noise of -97.9 dBc/Hz at the offset frequency of 100 kHz.

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Design of 5.5 GHz Band Oscillator for local wireless Communication system (근거리 무선통신용 5.5 GHz 대역 발진기 설계)

  • 김갑기
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.4
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    • pp.787-792
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    • 2004
  • This paper shows the design, fabrication and performance of oscillator appled to 5.5GHz RF module for local wireless communication system. Super low noise HJ FET of NE3210S01 is used to obtain a good phase noise Performance. The design Parameters for the optimum operating performance are simulated with ADS simulation. The measured out Power is 10 dBm at 5.5GHz, the second harmonic suppression -31 dBc, and the phase noise characteristics -98.83 dBc at 100kHz offset frequency, respectively. This implemented oscillator is available to local wireless Communication system.

A Design of High Speed Infrared Optical Data Link IC (고속 적외선 광 송수신 IC 설계)

  • 임신일;조희랑;채용웅;유종선
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.12B
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    • pp.1695-1702
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    • 2001
  • This paper describes a design of CMOS infrared (IR) wireless data link IC which can be used in IrDA(Infrared Data Association) application from 4 Mb/s to 100 Mb/s The implemented chip consists of variable gain transimpedance amplifier which has a gain range from 60 dB to 100 dB, AGC (automatic gain control) circuits, AOC(automatic offset control) loop, 4 PPM (pulse position modulation) modulator/demodulator and DLL(delay locked loops). This infrared optical link If was implemented using commercial 0.25 um 1-poly 5-metal CMOS process. The chip consumes 25 mW at 100 Mb/s with 2.5 V supply voltage excluding buffer amplifier. The die area of prototype IC is 1.5 mm $\times$ 1 mm.

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Design of Dual-Band WLAN Transmitter with Frequency Doubler (주파수 체배기를 이용한 이중대역 무선 송신부 설계)

  • Roh, Hee-Jung
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.22 no.6
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    • pp.116-126
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    • 2008
  • This paper describes the Dual-band WLAN transmitter with 2.4[GHz], 5[GHz]. Dual-band WLAN transmitter was designed at 2.4[GHz] and 5[GHz]. The Dual-band WLAN transmitter has a amplifier which operate at 2.4[GHz] and 5[GHz] frequency and two VCO(Voltage Controlled Oscillator) or VCO has a wide scope of frequency. these problem cause a size and a power consumption, The Dual-band WLAN transmitter module was proposed to solve these. the transmitter was designed to get output signals of IEEE 802.11a's 5.8[GHz] band signal using frequency multiplication way or to act a amplifier about the 2.4[GHz] band signal of IEEE 802.11b/g, according to inputed frequency and bias voltage that a eve using single transmission block. The output spectrum get the improved specification of ACPR of 4[dB], 6[dB], 16[dB] at +11[MHz], +20[MHz], +30[MHz] offset of center frequency compared to no linearization, was satisfied to transmit spectrum mask of IEEE 802.11a wireless Lan.

Performance Enhancement of Hybrid Doherty Amplifier using Drain bias control (Drain 바이어스 제어를 이용한 Hybrid Doherty 증폭기의 성능개선)

  • Lee Suk-Hui;Lee Sang-Ho;Bang Sung-Il
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.5 s.347
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    • pp.128-136
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    • 2006
  • In this paper, design and implement 50W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of ideal Doherty power amplifier is distinguishable; however bias control for implementation of Doherty(GDCHD) amplifier is difficult. To solve the problem, therefore, GDCHD(Gate and Drain Control Hybrid Doherty) power amplifier is embodied to drain bias adjustment circuit to Doherty power amplifier with gate bias adjustment circuit. Experiment result shows that $2.11{\sim}2.17\;GHz$, 3GPP operating frequency band, with 57.03 dB gain, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and -40.45 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GDCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than Doherty power amplifier.

The implementation of Gate Control Hybrid Doherty Amplifier (효율개선을 위한 Gate 제어 Hybrid Doherty 증폭기 구현)

  • Son Kil-young;Lee Suk-hui;Bang Sung-il
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.3 s.333
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    • pp.1-8
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    • 2005
  • In this paper, design and implement 60W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of Doherty power amplifier is distinguishable; however implementation of assistance amplifer is difficult, though. To solve the problem, therefore, GCHD (Gate Control Hybrid Doherty) power amplifier is embodied to gate bias adjusament circuit of assistance amplifier to General Doherty power amplifier. Experiment result shows that $2.11\~2.17GHz$, 3GPP operating frequency band, with 62.55 dB gain, PEP output is 50,76 dBm, W-CDMA average power is 47.81 dBm, and -40.05 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than general power amplifier.