• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.112-117
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• 2004

In this paper, we propose a suitable multiplication architecture for cellular automata in a finite field $GF(2^m)$. Proposed least significant bit first multiplier is based on irreducible all one Polynomial, and has a latency of (m+1) and a critical path of $ 1-D_{AND}＋1-D{XOR}$.Specially it is efficient for implementing VLSI architecture and has potential for use as a basic architecture for division, exponentiation and inverses since it is a parallel structure with regularity and modularity. Moreover our architecture can be used as a basic architecture for well-known public-key information service in $GF(2^m)$ such as Diffie-Hellman key exchange protocol, Digital Signature Algorithm and ElGamal cryptosystem.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.9-17
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• 2013

In this paper, we propose a new multiplication algorithm for two polynomials using primitive polynomial with all 1 of coefficient on finite fields GF($2^m$), and design the multiplier with high-speed parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $m^2$ same basic cells that have a 2-input XOR gate and a 2-input AND gate. Since the basic cell have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $D_A+D_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.709-711
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• 2001

본 논문에서는 유한 확대 체 GF($^{m}$ )상에서 셀룰라 오토마타를 이용한 곱셈기 구조를 제안한다. 제안된 구조는 기약 다항식으로 AOP(All One Polynomial)의 특성을 사용하고 LSB방식으로 곱셈 연산을 수행한다. 제안된 곱셈기는 지연시간으로 m+1을 갖는 임계경로로는 1- $D_{AND}$+1- $D_{XOR}$를 갖는다. 특히 구조가 정규성, 모듈성, 병렬성을 가지기 때문에 VLSI구현에 효율적이다.적이다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.35-42
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• 2001

The primitive polynomial on GF(q) is used in the area of the scrambler, the error correcting code and decode, the random generator and the cipher, etc. The algorithm that generates efficiently the primitive polynomial on GF(q) was proposed by A.D. Porto. The algorithm is a method that generates the sequence of the primitive polynomial by repeating to find another primitive polynomial with a known primitive polynomial. In this paper, we propose the algorithm that is improved in the A.D. Porto algorithm. The running rime of the A.D. Porto a1gorithm is O($\textrm{km}^2$), the running time of the improved algorithm is 0(m(m+k)). Here, k is gcd(k, $q^m$-1). When we find the primitive polynomial with m odor, it is efficient that we use the improved algorithm in the condition k, m>>1.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.710-717
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• 2010

Even though there are 256 possible 1-qudit(1-variable quantum digit) functions in quaternary logic, the most useful functions are 4!=24 ones capable of representing in QGFSOP expressions by possible permuting of 0,1,2, and 3. In this paper, we propose a permutational literal(PL) representation and a QPL(Quaternary PL) gate which use the operands of a multiplicand A and an augend D in $Ax^C$+D(GF4) operation as a control variable of multi-cascaded PLs. And we also present new PL synthesis algorithms to synthesize QGFSOP expressed 24 (1-qudit) functions by applying three PL operators as ab(mutual permutation), + D(addition), and XA (multiplication). Finally architectures, circuits, and a CMOS implementation to realize proposed PL synthesis algorithms for $Ax^C$+D(GF4) functions are presented.

• Korean Journal of Food Science and Technology
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• v.31 no.2
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• pp.448-457
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• 1999

Citrus fruits are consumed worldwide due to their unique flavor and nutrition value. It is necessary to remove the haze material as well as to minimize the loss of major compounds such as organic acids, sugars, and ascorbic acid in membrane processes for clarification of juice. The objective of our research was to select the best membrane among one surface filter (Whatman No.4) and five microfiltration filters (GF/A, GF/D, GF/F, Gelman, and SM). Tangerine fresh blended with three times of water was partially clarified with 170 mesh followed by prefiltration in a Samduck filtration system. The best membrane was selected by measuring the amounts of major compounds in the permeates as well as the flux which were statistically analyzed with SAS program. The foulants on the membrane surface were observed by SEM. The flux of GF/A and GF/F decreased with time at probability 0.10. Gelman, SM, and GF/D maintained the stable flux. Gelman showed the highest total scores including nutritive value (the amounts of citrate, malate, and ascorbic acid) and purchasing need (brix and color). Therefore, the microfiltration membrane process was a very effective method in tangerine juice clarification and Gelman type A/E was proved to be the best membrane among the five microfiltration membranes.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.45-52
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• 2002

In this contributions, we propose a new MSB(most significant bit) algorithm based on AOP(All One Polynomial) and two parallel semi-systolic architectures to computes $AB^2$over finite field $GF(2^m)$. The proposed architectures are based on standard basis and use the property of irreducible AOP(All One Polynomial) which is all coefficients of 1. The proposed parallel semi-systolic architecture(PSM) has the critical path of $D_{AND2^+}D_{XOR2}$ per cell and the latency of m+1. The modified parallel semi-systolic architecture(WPSM) has the critical path of $D_{XOR2}$ per cell and has the same latency with PSM. The proposed two architectures, PSM and MPSM, have a low latency and a small hardware complexity compared to the previous architectures. They can be used as a basic architecture for exponentiation, division, and inversion. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation. They can be used as a basic architecture for algorithms, such as the Diffie-Hellman key exchange scheme, the Digital Signature Algorithm(DSA), and the ElGamal encryption scheme which are needed exponentiation operation. The application of the algorithms can be used cryptosystem implementation based on elliptic curve.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.1 s.307
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• pp.1-8
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• 2006

This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.161-166
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• 2008

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF($2^m$) using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.