• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.188-198
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• 1993

We have developed a technique for growing thin oxides (6~10 nm) by the Last step TCA method. N-channel metal-oxide-semiconductor (n-MOS) capacitor and n-channel metal-oxide-semiconductor field-effect transistor's (MOSFET's) having a gate oxide with chlorine incorporated $SiO_2/Si$ interface have been analyzed by electrical measurements and physical methods, such as secondary ion mass spectrometry (SIMS) and electron spectroscopy for chemical analysis (ESCA). The gate oxide grown with the Last strp TCA method has good characteristics as follows: the electron mobility of the MOSFET's with the Last step TCA method was increased by about 7% and the defect density at the $SiO_2/Si$ interface decreases slightly compared with that with No TCA method. In reliability estimation, the breakdown field was 18 MV/cm, 0.6 MV/cm higher than that of the gate oxide with No TCA method, and the lifetime estimated by TDDB measurement was longer than 20 years. The device lifetime estimated from hot-carrier reliability was proven to be enhanced. As the results, the gate oxide having a $SiO_2/Si$ interface incorporated with chlorine has good characteristics. Our new technique of Last step TCA method may be used to improve the endurance and retention of MOSFET's and to alleviate the degradation of thin oxides in short-channel MOS devices.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.134.2-134.2
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• 2017

최근 고성능, 저 전력 반도체 소자를 위한 미세 공정 기술이 발전함에 따라, gate oxide의 두께 및 선폭이 감소하고, aspect ratio가 증가하고 있는 추세이다. 따라서 얇아진 gate oxide를 통한 채널 물질로의 boron 확산을 막기 위한 고농도 질화 막 증착의 필요성이 높아지고 있으며, high aspect ratio의 gate oxide에 적용 가능한 우수한 step coverage의 질화막 또한 요구되고 있다. 이러한 요구조건을 만족시키기 위해 일반적인 13.56MHz의 플라즈마 소스를 이용한 질화연구들이 선행되어져 왔으나, 높은 binding energy(~24 eV)를 가지고 있는 N2 molecule gas를 효과적으로 dissociation 하지 못해 충분한 질화공정이 수행되어질 수 없었을 뿐만 아니라 높은 공정온도($>200^{\circ}C$에서 진행되어 반도체소자에 손상을 줄 수 있다. 본 연구에서는 이러한 문제들을 해결하기 위해 VHF (162MHz)를 이용한 플라즈마를 통해 고밀도에서 낮은 전자온도와 높은 진동온도의 플라즈마를 구현하여 20%이상의 높은 질화율을 얻을 수 있었고, multi-tile push-pull 플라즈마 소스를 통해 VHF 사용 시 나타나는 standing wave effect를 제어하여 high aspect ratio의 gate sidewall spacer에 우수한 step coverage의 질화막을 형성시킬 수 있었다.

• Korean Journal of Materials Research
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• v.6 no.4
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• pp.395-400
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• 1996

반도체 소자가 점점 고집적회되고 고성능화되면서 Si 기판 세정 방법은 그 중요성이 더욱 더 커지고 있다. 특히 ULSI급 소자에서는 세정 방법이 소자 생산수율 및 신뢰성에 큰 영향을 끼치고 있다. 본 연구에서는 HF-last 세정에 UV/O3과 SC-1 세정을 삽입하여 그 영향을 관찰하였다. 세정 방법은 HF-last 세정을 기본으로 split 1(piranha+HF), split 2(piranha+UV/O3+HF), split 3(piraha+SC-1+HF), split 4(piranha+(UV/O3+HF) x3회 반복)의 4가지 세정 방법으로 나누어 실험하였다. 세정을 마친 Si 기판은 Total X-Ray Fluorescence Spectroscopy(AFM)을 사용하여 표면거칠기를 측정하였다. 또한 세정류량을 측정하고, Atomic Force Microscopy(AFM)을 사용하여 표면거칠기를 측정하였다. 또한 세정후 250$\AA$의 gate 산화막을 성장시켜 전기적 특성을 측정하였다. UV/O3을 삽입한 split 2와 split 4세정방법이 물리적, 전기적 특성에서 우수한 특성을 나타냈고, SC-1을 삽입한 split 3세정 방법이 표준세정인 split 1세정 방법보다 우수하지 못한 결과를 나타냈다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.79-87
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• 1998

Nitrided oxides which have been investigated as alternative gate oxide for metal-oxide-semiconductor field effect devices were grown by two-step process using N$_{2}$O gas, and were chaacterized via a fowler-nordheim tunneling(FNT) electron injection technique. Electrical characteristics of nitrided gate oxides were superior to that of control oxides.Further, the FNT electron injection into the nitrided gate oxides reveals that gate oxides degrade more both if electrons were foreced to inject from the gate metal and if thicker nitrided gate oxides were used in the thickness range of 90~130.angs.. Models are suggested to explain these phenomena.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.130-131
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• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.406-406
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• 2010

일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Applied Chemistry for Engineering
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• v.20 no.1
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• pp.99-103
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• 2009

HBr and $O_2$ in $Cl_2$ gas ambient for the high density plasma gate etching has been used to increase the performance of gate electrode in semiconductor devices. When an un-doped amorphous silicon layer was used for a gate electrode material, the notching profile was observed at the outer sidewall foot of the outermost line. This phenomenon can be explained by the electron shading effect: i.e., electrons are captured at the photoresist sidewall while ions pass through the photoresist sidewall and reach the oxide surface at a narrowly spaced pattern during the over etch step. The potential distribution between gate lines deflects the ions trajectory toward the gate sidewall. In this study, an appropriate mechanism was proposed to explain the occurrence of notching in the gate electrode of un-doped amorphous silicon.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.4
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• pp.282-285
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• 2019

A 100-nm gate-length metamorphic high electron mobility transistor(mHEMT) with a T-shaped gate was fabricated using a two-step gate recess and characterized for DC and microwave performance. The mHEMT device exhibited DC output characteristics having drain current($I_{dss}$), an extrinsic transconductance($g_m$) of 1,090 mS/mm and a threshold voltage($V_{th}$) of -0.65 V. The $f_T$ and $f_{max}$ obtained for the 100-nm mHEMT device were 190 and 260 GHz, respectively. The developed mHEMT will be applied in fabricating W-band monolithic microwave integrated circuits(MMICs).