• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• Journal of IKEEE
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• v.17 no.3
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• pp.275-283
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• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.795-798
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• 2007

In this paper, we propose an image reconstruction method utilizing an optimized adaptive interpolation kernel along with a 2D M-channel perfect reconstruction filter bank (M-ch PR-FB) structure. In particular, the proposed approach leads to construction of a sharper image than a direct conversion, still preserving high frequency components of the original image through the subband processing of the 2D M-ch PR-FB. Finally, the image quality of the proposed approach is demonstrated by comparing with those of the direct methods using conventional interpolation kernels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.2
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• pp.47-54
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• 1982

In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.2
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• pp.274-279
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• 2009

H.264 suggests applying a 2-D 6-tap wiener filter to realize the interpolation for half-pixel positions, followed by a bilinear interpolation to get the data of quarter-pixels precision. This method is comparatively simpler; however, it only considers the affection of 4-connection neighborhood ignoring the influence that comes from the changing rate between respective neighborhoods. As a result, it has the characteristics of a Low-pass filter under the risk of losing high-frequency weights. The Cubic interpolation uses the gray-values within the larger regions of points to be sampled for interpolation. Nevertheless, the cubic interpolation is more complicated and computational. We give a deep analysis on the features while applying both bilinear and cubic interpolation in H.264 presenting a proper selection of interpolation algorithm with respect to specific distribution of gray-value in a certain grand block. The experiments point out that load far motion searching and interpolation are reduced when promoting the precision of interpolation simultaneously.

• The KIPS Transactions:PartB
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• v.10B no.3
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• pp.339-346
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• 2003

In this paper, we propose a new method in which interpolation images are created by using a small number of axiai T2-weighted images instead of using many sectional images for 3D visualization of brain MR images. For image Interpolation, an important part of this process, we first segment a region of interest (ROI) that we wish to apply 3D reconstruction and extract the boundaries of segmented ROIs and MBR information. After the image size of interpolation layer is determined according to the changing rate of MBR size between top slice and bottom slice of segmented ROI, we find the corresponding pixels in segmented ROI images. Then we calculate a pixel's intensity of interpolation image by assigning to each pixel intensity weights detected by cube interpolation method. Finally, 3D reconstruction is accomplished by exploiting feature points and 3D voxels in the created interpolation images.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.931-934
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• 1998

We have implemented a sign language animation system using 2D and 3D models. From the previous studies, we find out that both models have several limitations based on the linear interpolation and fixed number of frames, and they result in incorrectness of actions and unnatural movements. To solve the problems, in this paper, we propose a sign language animation system using spline interpolation method and variable number of frames. Experimental results show that the proposed method could generate animation more correctly and rapidly than previous methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.618-633
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• 2000

In this paper, a Gaussian interpolation filter and cubic interpolation filter are presented to do more accurate channel estimation compared to the conventional linear interpolation filter for COFDM systems. In addition to an interpolation filter, a low pass filter using FFT and IFFT is also presented to reduce the noisy components of a channel estimate obtained by an interpolation filter. Channel estimates after low-pass filtering combined with interpolation filters can lower the error floor compared to the use of only interpolation filters. Computer simulation demonstrates that the presented channel estimation methods exhibit an improved performance compared to the conventional linear interpolation filter for COFDM systems in time-varying multipath fading channel and0.1 ~ 0.2 dB of Eb/No difference at BER=10-4 when the perfect channel estimation is compared.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2785-2788
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• 2001

In this paper, we present a new interpolation scheme for image enhancement using fuzzy inference. In general, interpolation techniques are based on linear operators which are essentially lowpass filters, hence, they tend to blur fine details in the original image. In our approach, the operator itself balances the strength of its sharpening and noise suppressing components according to the properties of the input image data.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.