• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.473-476
• /
• 2003

We suggest 2 dimensional Fast Fourier Transform using Polynomial Transform and integer Fast Fourier Transform. Unlike conventional 2D-FFT using the direct quantization of twiddle factor, the suggested 2D-FFT adopts implemented by the lifting so that the suggested 2D-FFT is power adaptable and reversible. Since the suggested FFT performg integer-to-integer mapping, the transform can be implemented by only bit shifts and auditions without multiplications. In addition. polynomial transform severely reduces the multiplications of 2D-FFT. While preserving the reversibility, complexity of this algorithm is shown to be much lower than that of any other algorithms in terms of the numbers of additions and shifts.

• ETRI Journal
• /
• v.45 no.6
• /
• pp.1035-1045
• /
• 2023

We propose a novel graphics processing unit (GPU) algorithm that can handle a large-scale 3D fast Fourier transform (i.e., 3D-FFT) problem whose data size is larger than the GPU's memory. A 1D FFT-based 3D-FFT computational approach is used to solve the limited device memory issue. Moreover, to reduce the communication overhead between the CPU and GPU, we propose a 3D data-transposition method that converts the target 1D vector into a contiguous memory layout and improves data transfer efficiency. The transposed data are communicated between the host and device memories efficiently through the pinned buffer and multiple streams. We apply our method to various large-scale benchmarks and compare its performance with the state-of-the-art multicore CPU FFT library (i.e., fastest Fourier transform in the West [FFTW]) and a prior GPU-based 3D-FFT algorithm. Our method achieves a higher performance (up to 2.89 times) than FFTW; it yields more performance gaps as the data size increases. The performance of the prior GPU algorithm decreases considerably in massive-scale problems, whereas our method's performance is stable.

• Journal of IKEEE
• /
• v.25 no.4
• /
• pp.697-702
• /
• 2021

Fast Fourier Transform (FFT) is a major signal processing block being widely used. For long-point FFT processing, usually more than 1024 points, its low-complexity implementation becomes very important while retaining high SQNR (Signal-to-Quantization Noise Ratio). In this paper, we present a low-complexity FFT algorithm with a simple dynamic scaling scheme. For the 2048-point pipelined FFT processing, we can reduce the number of general multipliers by half compared to the well-known radix-2 algorithm. Also, the table size for twiddle factors is reduced to 35% and 53% compared to the radix-2 and radix-2² algorithms respectively, while achieving SQNR of more than 55dB without increasing the internal wordlength progressively.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.4
• /
• pp.1278-1284
• /
• 2010

In this paper, we propose a new mura detection algorithm for TFT-LCD effectively, which is based on multi-point, 2-dimensional FFT. Since mura in TFT-LCD has a certain area shape, it is seen as a sin wave in a LCD line. Since shapes of mura can be seen a circle, horizontal oval, or vertical oval, it is shown that they can be detected by 2-dimensional FFT easily. Through simulation for test image, it is shown that proposed algorithm can detect various sizes of mura. The proposed algorithm can be utilized in automatic test equipment for effective TFT-LCD mura detection.

• The korean journal of orthodontics
• /
• v.47 no.2
• /
• pp.108-117
• /
• 2017

Objective: To investigate the effects of frontal facial type (FFT) and sex on preferred chin projection (CP) in three-dimensional (3D) facial images. Methods: Six 3D facial images were acquired using a 3D facial scanner (euryprosopic [Eury-FFT], mesoprosopic [Meso-FFT], and leptoprosopic [Lepto-FFT] for each sex). After normal CP in each 3D facial image was set to $10^{\circ}$ of the facial profile angle (glabella-subnasale-pogonion), CPs were morphed by gradations of $2^{\circ}$ from normal (moderately protrusive [$6^{\circ}$], slightly protrusive [$8^{\circ}$], slightly retrusive [$12^{\circ}$], and moderately retrusive [$14^{\circ}$]). Seventy-five dental students (48 men and 27 women) were asked to rate the CPs ($6^{\circ}$, $8^{\circ}$, $10^{\circ}$, $12^{\circ}$, and $14^{\circ}$) from the most to least preferred in each 3D image. Statistical analyses included the Kolmogorov-Smirnov test, Kruskal-Wallis test, and Bonferroni correction. Results: No significant difference was observed in the distribution of preferred CP in the same FFT between male and female evaluators. In Meso-FFT, the normal CP was the most preferred without any sex difference. However, in Eury-FFT, the slightly protrusive CP was favored in male 3D images, but the normal CP was preferred in female 3D images. In Lepto-FFT, the normal CP was favored in male 3D images, whereas the slightly retrusive CP was favored in female 3D images. The mean preferred CP angle differed significantly according to FFT (Eury-FFT: male, $8.7^{\circ}$, female, $9.9^{\circ}$; Meso-FFT: male, $9.8^{\circ}$, female, $10.7^{\circ}$; Lepto-FFT: male, $10.8^{\circ}$, female, $11.4^{\circ}$; p < 0.001). Conclusions: Our findings might serve as guidelines for setting the preferred CP according to FFT and sex.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.05a
• /
• pp.253-256
• /
• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• 제어로봇시스템학회:학술대회논문집
• /
• 1987.10a
• /
• pp.851-856
• /
• 1987

A direct computation algorithm of two dimensional fast Fourier transform (2D-FFT) is considered here for implementation in mesh connected multiprocessor array of both a 2D-toroidal and a rectangular type. Results are derived for a hardware algorithm including data allocation and interprocessor communications. A performance comparison is carried out between the proposed direct 2D-FFT computation and the conventional one to show that a new algorithm gives higher speedup under a reasonable assumption on the speeds of operations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.10a
• /
• pp.393-396
• /
• 2009

This paper describes a design of variable-length FFT/IFFT processor for OFDM-based communication systems. The designed FFT/IFFT processor adopts the in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate FFT lengths of $N=64{\times}2^k$ ($0{\leq}k{\leq}7$). To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The processor synthesized with a $0.35-{\mu}m$ CMOS cell library can operate with 75-MHz@3.3-V clock, and 64-point and 8,192-point FFT's can be computed in $2.55-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of wireless LAN, DMB, and DVB systems.

• The Journal of the Acoustical Society of Korea
• /
• v.14 no.2
• /
• pp.30-39
• /
• 1995

In this paper, study on implementation of FFT analyzer applied to CAT, A/D conversion module, DSP module and VXIbus interface module are implemented in hardware and calculation program and control software are implemented in DSP module and VXIbus interface module, respectively. The control of the modules using PC is realized in software. The real time bandwidth of the FFT analyzing device is 100KHz. At sampling rate of 200KHz and with 2048 point FFT, the result of applying sine, triangular and rectangular wave of 20KHz to FFT analyzing device is compared with the FFT analyzed results of Hewlett-Packard 3562A dynamic output range of -40dBV- +30dBV, correct results are obtained and results of applying 10KHz, 20KHz and 50KHz input are compared and the correct values are obtained.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.2A
• /
• pp.209-215
• /
• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.