• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.1
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• pp.128-141
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• 1994

This roport explain the basic theory of desinging the accelerating durability test road and the role of each factors contributing to test road surface profile. Also this road is designed by considering the charactors of vehicle suspension system and condition of driving. In test road, the factors affecting to the vehicle Structural durability are correlation among surface shape of road profile, frequency of vehicle suspension system, distribution of axletwist angle and vibration profile height Road PSD magnitude and frequency delay is used to control these factors relation.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.373-375
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• 1997

In this study, we designed multiple mesh circuit consisting of 3-6 meshes and pulse superposition one consisting of a 3 mesh, and fabricated the electrical power supply and the single elliptical resonator. We developed the two pulse superposition technique forming the step pulse shapes of pulsed Nd:YAG laser with single shot multivibrator and 2 SCRs. Laser beam generated by multiple mesh circuit and superposition one respectively irradiated target surface to analyze process state of surface with spark and vapor. And it was obtained experimental results that all superposition meshes had common points which the best efficiency was obtained at delay time 0[${\mu}s$], followed by, no superposition and obtained at delay time 250[${\mu}s$].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.1
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• pp.6-12
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• 2004

Identification rate and time are very important in the identification of RFID tag, and the tag requires simple structure to use economically large quantity of tags. These factors make the MAC protocols of wired or wireless network environment result in different requirements. In the paper, we propose a method to apply spread spectrum scheme using orthogonal channel via Walsh function as the anti-collision communication system for the purpose of non-collision identification of multiple tags, and consider its property. The proposed system use two step identification. in the first step, collision is resolved via constructing to respond after specific delay time based on unique n, and conventional polling scheme follows in the second step.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.523-530
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• 2016

We use both theoretical analysis and simulations to study the impact of crosspoint-queued (CQ) buffer size on CQ switch throughput and delay performance under different traffic models, input loads, and scheduling algorithms. In this paper, we present the following. 1) We prove the stability of CQ switch using any work-conserving scheduling algorithm. 2) We present an exact closed-form formula for the CQ switch throughput and a non-closed-form but convergent formula for its delay using static non-work-conserving random scheduling algorithms with any given buffer size under independent Bernoulli traffic. 3) We show that the above results can serve as a conservative guide on deciding the required buffer size in pure CQ switches using work-conserving algorithms such as the random scheduling, under independent Bernoulli traffic. 4) Furthermore, our simulation results under real-trace traffic show that simple round-robin and random work-conserving algorithms can achieve quite good throughput and delay performance with a feasible crosspoint buffer size. Our work reveals the impact of buffer size on the CQ switch performance and provides a theoretical guide on designing the buffer size in pure CQ switch, which is an important step toward building ultra-high-speed switch fabrics.

• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.79-92
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• 1995

In this paper we present an efficient parallel simulation algorithm in recursive feedforward network(RFN) which can reduce the simulation delay while decreasing the number of null messages compared to the previous result. As a preprocessing step, we first determine the group and type of each oupput channel for the nodes using DFS(Depth First Search) algorithm, and show that the number of null messages as well as the simulation scheme. By the new scheme we decide if null messages are sent to the output channels or not according to the group to which it belongs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.12
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• pp.1903-1910
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• 2012

This paper presents a data based low-order controller design algorithm for a linear time-invariant process with a time delay. The algorithm is composed by combining an identification step based on open loop pulse test with a low-order controller design step to obtain the entire set of controllers achieving multiple performance specifications. The initial information necessary for this algorithm are merely the width and amplitude of a rectangular pulse, a controller of four types (PI, PD, PID, first-order), and design objectives. Various parametric approaches that have been developed are merged in the controller design algorithm. The resulting controller set satisfying the design objectives are displayed on the 2D and 3D graphics and thus it is very easy for us to pick a controller inside the admissible set because we can check the corresponding closed-loop performances visually.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.382-389
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• 1995

In this paper, we propose an efficient transmission schedule which can be used in indoor wireless LAN. It reduces considerably the time delay and increases the throughput by reusing the bandwidth. We describe the architecture of the wireless LAN, the algorithm of step-by-step allocation of time slot reusing the resource and the results of the computer simulation.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2001.11a
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• pp.112-119
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• 2001

Parameter tuning methods by Ziegler-Nickels for control systems are generally classified into Z-N(1) and Z-N(2). The purpose of this paper is to describe what relations exist between methods of Z-N(1) and Z-N(2), or how Z-N(1) method can be originated from Z-N(2) method by analyzing one loop control system of P or PI controller and time delay process. The formulas of Z-N(1) consist of process parameters, L(time delay), $K_m$(gain) and $T_m$(time constant), but Z-N(2) method is based only on the ultimate gain $K_u$ and the ultimate period $T_u$ acquired normally by practical trial without any parameters of Z-N(1). In this paper, for the first step to seek mutual relations, the simple formulas of Z-N(2) are transformed into the formulas composed of the same parameters as Z-N(1) which is derived from the analysis of frequency characteristics. Then, the approximation of the actual ultimate frequency is proposed as important premise in the translation between Z-N(1) and (2). Such equalization and approximation brings a simple approximated formula which can explain how Z-N(1) is originated from the Z-N(2) in the form of formula. And a model system is adopted to compare the approximated formula to Z-N(1) and Z-N(2) methods, the results of which show the effectiveness of the proposals.

• ETRI Journal
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• v.38 no.2
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• pp.217-226
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• 2016

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second-order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal-shape half-delayed return-to-zero feedback DAC eliminates the loop-delay compensation circuitry and improves pulse-delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of $0.098mm^2$ and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure-of-merit of the modulator is 191 fJ/conversion-step.