• Title/Summary/Keyword: 16 bit communication

Search Result 249, Processing Time 0.031 seconds

A Design of 16${\times}$16-bit Redundant Binary MAC Using 0.25 ${\mu}{\textrm}{m}$ CMOS Technology

  • Kim, Tae-Min;Shin, Gun-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.7 no.1
    • /
    • pp.122-128
    • /
    • 2003
  • In this paper, a 16${\times}$16-bit Multiplier and Accumulator (MAC) is designed using a Redundant Binary Adder (RBA) circuit so that it can make a fast addition of the Redundant Binary Partial Products (RB_PP's) by using Wallace-tree structure. Because a RBA adds two RB numbers, it acts as a 4-2 compressor, which reduces four inputs to two output signals. We propose a method to convert the Redundant Binary (RB) representation into the 2's complement binary representation. Instead of using the conventional full adders, a more efficient RB number to binary number converter can be designed with new conversion method.

16-QAM-Based Highly Spectral-Efficient E-band Communication System with Bit Rate up to 10 Gbps

  • Kang, Min-Soo;Kim, Bong-Su;Kim, Kwang Seon;Byun, Woo-Jin;Park, Hyung Chul
    • ETRI Journal
    • /
    • v.34 no.5
    • /
    • pp.649-654
    • /
    • 2012
  • This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

Performance Analysis of 3/4 TC 16Qam in Rading Channel (페이딩 채널에서의 3/4 TC 16QAM의 성능 분석)

  • 정구영;문재경;김창주;김영수
    • The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.6 no.2
    • /
    • pp.45-53
    • /
    • 1995
  • In mobile communication, the performance of QAM technique is poor under deep fading even though Rayleigh channel characteristics are estimated and compensated. In this paper, we analyze the performance of 3/4 Trellis coded 16QAM in Rayleigh channel where burst errors are randomized by bit reversal block interleaver, and TCM coder is designed by computer search to be adequate for Rayleigh channel. The simulation results show that the interleaver has 2dB gain, the modified Viterbi decoder has 2.5dB, and diversity has 9dB gain at $P_{b}b/=10^{-3}$. This indicates that the 3/4 TC 16QAM is applicable to digital mobile communication with good performance.

  • PDF

Bit-selective Forward Error Correction for 14Kbps SBC-APCM (AQB) over Digital Mobile Communication Channels (디지털 이동통신 채널상의 14Kbps SBC-APCM(AQB)를 위한 비트선택적 에러정정부호)

  • 김민구;이재홍
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.27 no.6
    • /
    • pp.821-828
    • /
    • 1990
  • A forward error correction (FEC) technique is presented for speech data in 16 Kbps digital mobile communications. 14Kbps SBC-APCM(AQB) and QPSK are used as speech coding and modulation techniques, respectively. Because each bit in a speech data block had different importance, applying FEC to speech data bit-selectively in more effective than applying FEC to all speech data equally. To select bits in a speech data block to be protected by FEC the bit error sensitivity of each bit is computed. For a few BCH and Reed-Solomon codes used as bit-selective FEC the performance of the coding technique is computed.

  • PDF

Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

  • Nguyen, Tuy Tan;Lee, Hanho
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.16 no.1
    • /
    • pp.118-125
    • /
    • 2016
  • This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

Exact Algorithms of Transforming Continuous Solutions into Discrete Ones for Bit Loading Problems in Multicarrier Systems

  • Chung, Yong-Joo;Kim, Hu-Gon
    • Management Science and Financial Engineering
    • /
    • v.16 no.3
    • /
    • pp.71-84
    • /
    • 2010
  • In this study, we present the exact methods of transforming the continuous solutions into the discrete ones for two types of bit-loading problem, marginal adaptive (MA) and rate adaptive (RA) problem, in multicarrier communication systems. While the computational complexity of existing solution methods for discrete optimal solutions depends on the number of bits to be assigned (R), the proposed method determined by the number of subcarriers (N), making ours be more efficient in most cases where R is much larger than N. Furthermore our methods have some strength of their simpler form to make a practical use.

Design and Implementation of a Power Aware Scalable Pipelined Booth Multiply & Accumulate Unit (소비전력 인지형 곱셈 연산 누적기의 설계 및 구현)

  • Shin, Min-Hyuk;Lee, Han-Ho
    • Proceedings of the IEEK Conference
    • /
    • 2006.06a
    • /
    • pp.573-574
    • /
    • 2006
  • A low-power power-aware scalable pipelined Booth recoded multiply & Accumulate unit (PA-MAC) detects the input operands for their dynamic range and accordingly implements a 16-bit, 8-bit or 4-bit multiplication and accumulation operation. The multiplication mode is determined by the dynamic - range detection unit. For the computations, although an area of the proposed PA-MAC is lager than a non-scalable MAC respectively, the proposed PA-MAC proves to be globally more power efficient than a non-scalable MAC.

  • PDF

Performance Analysis of a TransferJet System (TransferJet 시스템의 성능분석)

  • Park, Kyung-Won;Wee, Jeong-Wook;Seo, Jeong-Wook;Jeon, Won-Gi
    • Journal of Advanced Navigation Technology
    • /
    • v.16 no.5
    • /
    • pp.810-816
    • /
    • 2012
  • In this paper, BER(Bit Error Ratio) performances of the TransferJet system, which is the standard of a close proximity inductive wireless communication system, are presented and analyzed. Comparing to other wireless communication systems, the TransferJet system has some advantages such as short communication range(i.e., high security in the wireless communication environments), fewer effects of multipath distortion, and higher transmission rate. In order to demodulate the received signal, either SC(Soft-decision Combining) or HC(Hard-decision Combining) can apply to the despreader and demodulator of the receiver. When the spreading factor is more than 4, the SC scheme approximately has a minimum signal-to-noise ratio gain of 2 dB over the HC scheme. Moreover, from simulation results, we can conclude that the quantization bits of 3 bits are an optimum value for the SC scheme in the TransferJet system since the 3-bit quantization achieves nearly the performance as that attained by double-precision floating-point.

Reversible and High-Capacity Data Hiding in High Quality Medical Images

  • Huang, Li-Chin;Hwang, Min-Shiang;Tseng, Lin-Yu
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • v.7 no.1
    • /
    • pp.132-148
    • /
    • 2013
  • Via the Internet, the information infrastructure of modern health care has already established medical information systems to share electronic health records among patients and health care providers. Data hiding plays an important role to protect medical images. Because modern medical devices have improved, high resolutions of medical images are provided to detect early diseases. The high quality medical images are used to recognize complicated anatomical structures such as soft tissues, muscles, and internal organs to support diagnosis of diseases. For instance, 16-bit depth medical images will provide 65,536 discrete levels to show more details of anatomical structures. In general, the feature of low utilization rate of intensity in 16-bit depth will be utilized to handle overflow/underflow problem. Nowadays, most of data hiding algorithms are still experimenting on 8-bit depth medical images. We proposed a novel reversible data hiding scheme testing on 16-bit depth CT and MRI medical image. And the peak point and zero point of a histogram are applied to embed secret message k bits without salt-and-pepper.