• Title/Summary/Keyword: 10b/8b decoder.

Search Result 35, Processing Time 0.019 seconds

DCT-domain MPEG-2/H.264 Video Transcoder System Architecture for DMB Services (DMB 서비스를 위한 DCT 기반 MPEG-2/H.264 비디오 트랜스코더 시스템 구조)

  • Lee Joo-Kyong;Kwon Soon-Young;Park Seong-Ho;Kim Young-Ju;Chung Ki-Dong
    • The KIPS Transactions:PartB
    • /
    • v.12B no.6 s.102
    • /
    • pp.637-646
    • /
    • 2005
  • Most of the multimedia contents for DBM services art provided as MPEG-2 bit streams. However, they have to be transcoded to H.264 bit streams for practical services because the standard video codec for DMB is H.264. The existing transcoder architecture is Cascaded Pixel-Domain Transcoding Architecture, which consists of the MPEG-2 dacoding phase and the H.264 encoding phase. This architecture can be easily implemented using MPEG-2 decoder and H.264 encoder without source modifying. However. It has disadvantages in transcoding time and DCT-mismatch problem. In this paper, we propose two kinds of transcoder architecture, DCT-OPEN and DCT-CLOSED, to complement the CPDT architecture. Although DCT-OPEN has lower PSNR than CPDT due to drift problem, it is efficient for real-time transcoding. On the contrary, the DCT-CLOSED architecture has the advantage of PSNR over CPDT at the cost of transcoding time.

Dual-Band Six-Port Direct Conversion Receiver with I/Q Mismatch Calibration Scheme for Software Defined Radio (Software Defined Radio를 위한 I/Q 부정합 보정 기능을 갖는 이중 대역 Six-Port 직접변환 수신기)

  • Moon, Seong-Mo;Park, Dong-Hoon;Yu, Jong-Won;Lee, Moon-Que
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.21 no.6
    • /
    • pp.651-659
    • /
    • 2010
  • In this paper, a new six-port direct conversion receiver for high-speed multi-band multi-mode wireless communication system such as software defined radio(SDR) is proposed. The designed receiver is composed of two CMOS four-port BPSK receivers and a dual-band one-stage polyphase filter for quadrature LO signal generation. The four-port BPSK receiver, implemented in 0.18 ${\mu}m$ CMOS technology for the first time in microwave-band, is composed of two active combiners, an active balun, two power detector, and an analog decoder. The proposed polyphase filter adopt type-I architecture, one-stage for reduction of the local oscillator power loss, and LC resonance structure instead of using capacitor for dual-band operation. In order to extent the operation RF bandwidth of the proposed six-port receiver, we include I/Q phase and amplitude calibration scheme in the six-port junction and the power detector. The calibration range of the phase and amplitude mismatch in the proposed calibration scheme is 8 degree and 14 dB, respectively. The validity of the designed six-port receiver is successfully demonstrated by modulating M-QAM, and M-PSK signal with 40 Msps in the two-band of 900 MHz and 2.4 GHz.

Fine-scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec

  • Kim, Sunwoong;Jang, Ji Hun;Lee, Hyuk-Jae;Rhee, Chae Eun
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.17 no.3
    • /
    • pp.446-457
    • /
    • 2017
  • In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

Distributed Coding Scheme for Multi-view Video through Efficient Side Information Generation

  • Yoo, Jihwan;Ko, Min Soo;Kwon, Soon Chul;Seo, Young-Ho;Kim, Dong-Wook;Yoo, Jisang
    • Journal of Electrical Engineering and Technology
    • /
    • v.9 no.5
    • /
    • pp.1762-1773
    • /
    • 2014
  • In this paper, a distributed image coding scheme for multi-view video through an efficient generation of side information is proposed. A distributed video coding technique corrects the errors in the side information, which is generated with the original image, by using the channel coding technique at the decoder. Therefore, the more correct the generated side information is, the better the performance of distributed video coding. The proposed technique is to apply the distributed video coding schemes to the image coding for multi-view video. It generates side information by selectively and efficiently using both 3-dimensional warping based on the depth map with spatially adjacent frames and motion-compensated temporal interpolation with temporally adjacent frames. In this scheme the difference between the adjacent frames, the sizes of the motion vectors for the adjacent blocks, and the edge information are used as the selection criteria. From the experiments, it was observed that the quality of the side information generated by the proposed technique was improved by the average peak signal-to-noise ratio of 0.97dB than the one by motion-compensated temporal interpolation or 3-dimensional warping. The result from analyzing the rate-distortion curves revealed that the proposed scheme could reduce the bit-rate by 8.01% on average at the same peak signal-to-noise ratio value, compared to previous work.

A new spect of offset and step size on BER perfermance in soft quantization Viterbi receiver (연성판정 비터비 복호기의 최적 BER 성능을 위한 오프셋 크기와 양자화 간격에 관한 성능 분석)

  • Choi, Eun-Young;Jeong, In-Tak;Song, Sang-Seb
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.27 no.1A
    • /
    • pp.26-34
    • /
    • 2002
  • Mobile telecommunication systems such as IS-95 and IMT-2000 employ frame based communication using frames up to 20 msec in length and the receiving end has to store the whole frome before it is being processed. The size of the frame buffer ofter dominates those of the processing unit such as soft decision Viterbi decoder. The frame buffer for IMT-2000, for example, has to be increased 80 times as large as that of IS-95. One of the parameters deciding the number of bits in a frame will be obviously the number of bits in soft quantization. Start after striking space key 2 times. This paper has studied a new aspect of offset and quantization step size on BER performance and proposes a new 3-bit soft quantization algorithm which shows similar performance as that of 4-bit soft decision Viterbi receiver. The optimal offset values and step sizes for the other practical quantization levels ---16, 8, 4, 2--- have also been found. In addition, a new optimal symbol metric table has been devised which takes the accumulation value of various repeated signals and produces a rescaled 3-bit valu.tart after striking space key 2 times.