• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.812-820
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• 2006

Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique(not only LAN, but MAN and WAN) to ethernet. Performance evaluation was performed using C language for 10Gbps ethernet Data Link to design the optimum hardware, then internal FIFO size was evaluated. In this paper, MAC core for 10Gbps ethernet which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMII interface block was designed using VHDL language and Xilinx 6.2i tool and verified using Model_SIM 5.7G simulator. According to the specification of 10Gbps ethernet, MAC core with 64-bit data path should support 156.25MHz in order to support 10Gbps. The designed MAC core that process 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps data processing. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.547-554
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• 2005

Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique to ethernet. This paper studied the design of MAC which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMll interface block. Performance evaluation was performed using C language for 10cbps ethernet Data Link to design the optimum hardware, then internal FIFO and initial parameters were evaluated. When offered load is $95\%$, the size of the internal FIFO is required 512-word. When offered load is $97\%$, the size of the internal FIFO is required 1024-word. Based on the result of performance evaluation, MAC was designed in VHDL Language and verified using simulator. MAC core that processes 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.27-36
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• 2004

In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1601-1610
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• 2011

This paper discusses standardization activities, requirements and enabling technologies for 100G Ethernet and 100G OTN. The need of 100Gbps transport capacity has been gaining greater interest from service providers and carrier vendors. Moreover, optical transport networks based on OTN/DWDM are changing their properties to apply Ethernet traffic which is dramatically increasing. We realize and experimentally demonstrate OTU4 framer with commercial FPGA. The key features of the realized OTU4 framer are parallel signal processing function, multi-lane distribution function, GMP function and FEC function. The realized OTU4 framer has the large signal processing capacity of 120Gbps, which allows to transport about 120Gbps client signals such as $12{\times}10G$ Ethernet and $3{\times}40G$ Ethernet. The realized OTU4 framer has the advantages to quickly adjust to changing markets and new technologies by using commercial FPGA instead of ASIC.

• The Magazine of the IEIE
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• v.31 no.3
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• pp.49-56
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• 2004

지금까지 end-to-end ethernet 서비스를 실현하기 위한 노력으로 10 Gbps 이상의 ethernet 전송기술, 강력한 보안프로토콜, 그리고 QoS 방안 등이 주가 되어 연구되고 논의되어져 왔다. 본 고에서는 기존의 asynchronous ethernet을 그대로 수용하며 기존 ethernet의 가장 큰 한계점으로 지적되었던 real-time data전송문제를 해결하기 위한 ‘Synchronous Ethernet’ 의 표준화 현황 및 기술을 소개하고자 한다. ‘Synchronous Ethernet’은 현재 공식적으로 정해진 표준이 없는 상태지만 2004년에 국제표준회의에서 새롭고 활발한 활동으로 자리잡을 것으로 보인다.(중략)

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.862-865
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• 2011

지난 3 월 3 일 발생한 분산서비스 거부 공격의 경우 보안 패치 업데이트를 방해하는 현상이 신고되어 공격 시작 전에 악성코드가 분석됨으로 초동 대응이 가능하였다. 하지만 일반적인 분산서비스 거부 공격은 이러한 초동 분석이 불가능한 경우가 대부분이다. 따라서 네트워크에서 공격 트래픽을 효과적으로 탐지 차단하는 DDoS 탐지 엔진이 필요하다. 또한 빠른 트래픽 증가로 인하여 10Gbps Ethernet 사용이 일반화 되고 있고, 이미 수 백 Gbps 의 공격 트래픽이 수시로 발생하고 있다. 본 논문에서는 선로 속도 10Gbps 성능의 분산서비스거부 공격 탐지 칩 셋의 구현에 대해 기술한다. 칩 구현을 위한 고려 사항, 엔진 구조, 하드웨어 합성 결과 및 시스템에 장착된 칩의 성능에 대하여 소개하고자 한다.

• The Magazine of the IEIE
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• v.31 no.8
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• pp.32-43
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• 2004

이더넷(Ethernet)(［1］)은 현재 가장 널리 쓰이는 통신망용 프로토콜로써, 70년대말 10Mbps급의 속도를 제공하던 이더넷은 100Mbps, 1Gbps를 거쳐 현재는 10Gbps 제품들이 시장에 나오고 있다. 세계적으로 수억대 이상의 컴퓨터에서 이더넷 제품이 살이고 있으며, 이미 확립된 기반과 그에 따른 유지관리의 용이함 등에 힘입어 아직도 막대한 숫자로 채택되어 쓰이고 있고 앞으로 10/100Mbps 이더넷 제품들이 자연스럽게 1/10Gbps 제품군으로 업그레이드될 것으로 보인다.(중략)

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.674-677
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• 2004

최근 대부분의 전송기술(LAN 뿐만 아니라 MAN과 WAN까지)이 이더넷으로 통일되는 경향에 힘입어, 예전에 비하여 이더넷은 최근에 대단한 주목을 받게 되었다. 그러나 그동안 ATM 등의 전송기술에 의해 관심밖에 있던 이더넷이기 때문에, 국내에서 축적된 기술도 미약하다. 그리고, 이더넷이라는 기술은 단순한 디지털 로직이 아닌 디지털 / 아날로그 모뎀기술과 광 전송기술, 소프트웨어기술들이 결합된 고도의 전송기술이기 때문이다. 10Gbps 이더넷 표준이 2002년에 발표되면서 10Gbps 이더넷에 대해 많은 연구가 지속되고 있다. 10Gbps 이더넷의 특징은 이더넷 고유의 CSMA/CD 방식을 지원하지 않고, 점대점 전이중 방식만을 지원하고, 기존의 프레임구조는 계속 유지하였다. 본 연구에서는 10Gbps 이더넷 Data Link 계층의 MAC(Media Access Control) 코어를 C언어를 이용하여 성능평가를 실시하여 활용 가능한 응용분야와 내부 FIFO와 파라미터 초기 값을 도출하였다. 성능평가 결과 MAC 모듈은 짧은 패킷이 유입되었을 때 95%까지, 일반 패킷이 유입되었을 때 97%까지 패킷 손실이 발생하지 않음을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.577-585
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• 2004

System Packet Interface Level 4 Phase(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. In this paper, we performs the research for SPI-4.2. Also we analyze the performance of SPI-4.2 interface module after modeling using C programming language. This paper shows that SPI-4.2 interface module with 512-word FIFO depth is able to be adapted for the offered loads to 97％ in random uniform traffic and 94％ in bursty traffic with bursty length 32. SPI-4.2 interface module can experience an performance degradation due to heavy overhead when it massively receives small size packets less than 14-byte. SPI-4.2 interface module is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• ETRI Journal
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• v.28 no.1
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• pp.9-16
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• 2006

In this paper, we analyzed and measured the electrical crosstalk characteristics of a 1.25 Gbps triplexer module for Ethernet passive optical networks to realize fiber-tothe-home services. Electrical crosstalk characteristic of the 1.25 Gbps optical triplexer module on a resistive silicon substrate should be more serious than on a dielectric substrate. Consequently, using the finite element method, we analyze the electrical crosstalk phenomena and propose a silicon substrate structure with a dummy ground line that is the simplest low-crosstalk layout configuration in the 1.25 Gbps optical triplexer module. The triplexer module consists of a laser diode as a transmitter, a digital photodetector as a digital data receiver, and an analog photodetector as a cable television signal receiver. According to IEEE 802.3ah and ITU-T G.983.3, the digital receiver and analog receiver sensitivities have to meet -24 dBm at $BER=10^{-12}$ and -7.7 dBm at 44 dB SNR. The electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysis and measurement results, the proposed silicon substrate structure that contains the dummy line with $100\;{\mu}m$ space from the signal lines and 4 mm separations among the devices satisfies the electrical crosstalk level compared to a simple structure. This proposed structure can be easily implemented with design convenience and greatly reduce the silicon substrate size by about 50 %.