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A Study on MAC Core for 10Gbps Ethernet  

Sonh Seung-Il (한신대학교 정보통신학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.9, no.3, 2005 , pp. 547-554 More about this Journal
Abstract
Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique to ethernet. This paper studied the design of MAC which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMll interface block. Performance evaluation was performed using C language for 10cbps ethernet Data Link to design the optimum hardware, then internal FIFO and initial parameters were evaluated. When offered load is $95\%$, the size of the internal FIFO is required 512-word. When offered load is $97\%$, the size of the internal FIFO is required 1024-word. Based on the result of performance evaluation, MAC was designed in VHDL Language and verified using simulator. MAC core that processes 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.
Keywords
Ethernet; MAC(Media Access Control); Reconciliation; XCMII; VHDL; ModelSim;
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