• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.411-414
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• 2014

A switch is one of the most useful circuits for controlling the path of signal transmission. It can be added to digital circuits to create a kind of gate-level device and it can also save information into memory. In RF subsystems, a switch is used in a different way than its general role in digital circuits. The most important characteristic to consider when designing an RF switch is keeping the isolation as high as possible while also keeping insertion loss as low as possible. For high isolation, we propose leakage signal cancellation and inductive switching for designing a singlepole double-throw (SPDT) RF switch. By using the proposed method, an isolation level of more than 23 dB can be achieved. Furthermore, the heterojunction bipolar transistor (HBT) process is used in the RF switch design to keep the insertion loss low. It is demonstrated that the proposed RF switch has an insertion loss of less than 2 dB. The RF switch operates from 1 to 8 GHz based on the $0.18-{\mu}m$ SiGe HBT process, taking up an area of $0.3mm^2$.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1527-1530
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• 2009

A LCoS micro-display using polymer dispersed liquid crystals (PDLCs) for light switching layer was fabricated. The Si backplane of SVGA ($800{\times}600$) with a pixel size of $14{\times}14mm^2$ was prepared by a $0.35{\mu}m$ 18V CMOS process. PDLCs were filled in the gap between backplane and ITO glass by conventional vacuum filling method. The prepared panels were driven by a field sequential color (FSC) scheme at the frequency of 180Hz and were successful in modulating LED lights to show projection images. The preparation and performance of PDLC-LCoS are presented.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.501-512
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• 2018

Radio frequency identification (RFID) sensor tag provides several advantages including battery-less operation and low cost, which are suitable for long-term monitoring. This paper presents a self-powered RFID temperature sensor tag for online temperature monitoring in substation. The proposed sensor tag is used to measure and process the temperature of high voltage equipments in substation, and then wireless deliver the data. The proposed temperature sensor employs a novel phased-locked loop (PLL)-based architecture and can convert the temperature sensor in frequency domain without a reference clock, which can significantly improve the temperature accuracy. A two-stage rectifier adopts a series of auxiliary floating rectifier to boost its gate voltage for higher power conversion efficiency. The sensor tag chip was fabricated in TSMC $0.18{\mu}m$ 1P6M CMOS process. The measurement results show that the proposed temperature sensor tag achieve a resolution of $0.15^{\circ}C$/LSB and a temperature error of $-0.6/0.7^{\circ}C$ within the range from $-30^{\circ}C$ to $70^{\circ}C$. The proposed sensor tag achieves maximum communication distance of 11.8 m.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.542-549
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• 2016

This paper presents a SoC (System-on-a-Chip) dedicated for a single-chip smart capsule which can be used to continuously monitor human alimentary canal pH and temperature values. The SoC is composed of the pH and temperature sensor interface circuit, a wireless transceiver, the power management circuit and the flow control logic. Fabricated in $0.18{\mu}m$ standard CMOS technology, the SoC occupies a die area of ${\sim}9 mm^2$. The SoC consumes 6.15 mW from a 3 V power supply, guaranteeing the smart capsule battery life is no less than 24 hours when using 50 mAh coin batteries. The experimental results show that measurement accuracy of the smart capsule is ${\pm}0.1$ pH and ${\pm}0.2^{\circ}C$ for pH and temperature sensing, respectively, which meets the requirement of in-body pH and temperature monitoring in clinical practice.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.129-140
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• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• 한국정보통신학회논문지
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• 제21권6호
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• pp.1083-1091
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• 2017

NIST 표준에 정의된 소수체(prime field) GF(p) 상의 224-비트 타원곡선을 지원하는 타원곡선 암호 프로세서를 설계하였다. 타원곡선 암호의 핵심 연산인 스칼라 점 곱셈을 수정형 Montgomery ladder 알고리듬을 이용하여 구현하였다. 점 덧셈과 점 두배 연산은 투영(projective) 좌표계를 이용하여 연산량이 많은 나눗셈 연산을 제거하였으며, 소수체 상의 덧셈, 뺄셈, 곱셈, 제곱 연산만으로 구현하였다. 스칼라 점 곱셈의 최종 결과값은 다시 아핀(affine) 좌표계로 변환되어 출력하며, 이때 사용되는 역원 연산은 Fermat's little theorem을 이용하여 구현하였다. 설계된 ECC 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였다. $0.18{\mu}m$공정의 CMOS 셀 라이브러리로 합성한 결과 10 MHz의 동작 주파수에서 2.7-Kbit RAM과 27,739 GE로 구현되었고, 최대 71 MHz의 동작 주파수를 갖는다. 스칼라 점 곱셈에 1,326,985 클록 사이클이 소요되며, 최대 동작 주파수에서 18.7 msec의 시간이 소요된다.

• 정보보호학회논문지
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• 제17권1호
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• pp.11-20
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• 2007

몽고메리 곱셈 방법을 이용한 고속 연산은 RSA 암호 시스템의 설계에 중요한 부분을 차지한다. 몽고메리 곱셈은 두번의 덧셈 연산으로 구성되며 CSA를 이용한 방법과 RBA를 이용한 방법이 있다. CSA의 경우 4-2 CSA 또는 5-2 CSA를 이용하여 구현하며, RBA의 경우 기존 이진 방법과 달리 잉여 이진체계를 이용한다는 특징을 가진다. [1] 에서는 기존의 RBA와 다른 새로운 이진 체계와 하드웨어 구조를 제안하고 몽고메리 곱셈에 적용하였다. 본 논문에서는 [1] 에서 제안한 RBA의 로직 구조를 재구성하여 시간 복잡도 뿐만 아니라 결합기가 필요하지 않도록 구성하여 공간 복잡도를 크게 줄였다. 또한 입 출력 값을 변형시켜 지수승 연산에 적합하도록 설계하였다. 그 결과 제안하는 RBA는 삼성 STD130 $0.18{\mu}m$ 1.8V 표준 셀 라이브러리에서 지원하는 게이트들을 사용하여 설계하는 환경에서, 기존의 4-2 CSA 보다 공간과 시간 복잡도를 각각 18.5%와 25.24%를, 기존의 RBA 보다 6.3%와 14%를 감소시킨다. 또한 [1] 의 RBA와 비교시 44.3%, 2.8%의 감소된 복잡도를 갖는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.232-239
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• 2010

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.