• 대한전자공학회논문지SD
• /
• 제45권2호
• /
• pp.28-33
• /
• 2008

본 논문에서는 클록 손실 측정 기법을 이용한 디지털 디스플레이 인터페이스(Digital Display Interface: DDI)용 이퀄라이저를 제안한다. 제안하는 클록 손실 측정 기법은 최저 전압 유지 회로를 사용하여서 채널의 손실 정보를 추출한다. 추출된 손실 정보는 이퀄라이저 필터에 인가되며, 시스템의 안정도를 증가시키기 위해 제안된 이퀄라이저는 피드포워드 구조(Feedforward Loop)로 구현된다. 제안된 이퀄라이저는 0.18um CMOS 공정으로 제작되었으며, 실험 결과 채널 손실이 -33dB인 경우에 1.65Gbps의 신호들이 최소 0.7UI의 Eye Width를 가지게 된다. 또한 최대 10mW 이하의 전력을 소모하며, $0.127mm^2$ 의 유효면적을 차지한다.

• ETRI Journal
• /
• 제36권1호
• /
• pp.141-150
• /
• 2014

A fully integrated CMOS security-enhanced passive (SEP) tag that compensates the security weakness of ISO/IEC 18000-6C is presented in this paper. For this purpose, we propose a security-enhanced protocol that provides mutual authentication between tag and reader. We show that the proposed protocol meets the security demands of the ongoing international standard for RFID secure systems, ISO/IEC 29167-6. This paper fabricates the SEP tag with a 0.18-${\mu}m$ CMOS technology and suggests the optimal operating frequency of the CMOS SEP tag to comply with ISO/IEC 18000-6C. Furthermore, we measure the SEP tag under a wireless environment. The measured results show that communications between the SEP tag and reader are successfully executed in both conventional passive and SEP modes, which follow ISO/IEC 18000-6C and the proposed security enhanced protocol, respectively. In particular, this paper shows that the SEP tag satisfies the timing link requirement specified in ISO/IEC 18000-6C.

• 센서학회지
• /
• 제23권2호
• /
• pp.87-93
• /
• 2014

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 ${\mu}m$ process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

• 센서학회지
• /
• 제26권4호
• /
• pp.223-227
• /
• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2016년도 춘계학술대회
• /
• pp.691-692
• /
• 2016

본 논문은 802.11a 무선 랜용 5.25-GHz BiCMOS 저 잡음 증폭기를 제안한다. 이러한 회로는 1볼트 전원에서 동작하며, 저 전압 전원 공급에서도 높은 전압 이득을 가지도록 설계하였다. 제안한 회로는 $0.18{\mu}m$ SiGe HBT BiCMOS로 설계되어 있다. 저 전압 및 저 전력 동작을 위해 바이어스 회로는 밴드 갭 참조 (band-gap reference circuit) 바이어스 회로를 사용하였다. 제안한 회로는 최근 발표된 연구결과에 비해 높은 전압이득, 낮은 잡음지수 및 작은 칩 크기 특성을 보였다.

• 전기학회논문지
• /
• 제58권5호
• /
• pp.999-1003
• /
• 2009

We have designed and fabricated a linear drive amplifier with a novel intermodulation distortion(IMD) canceller using $0.18{\mu}m$ CMOS process. The drive amplifier with IMD canceller is composed of a cascode main amplifier and an additional common-source IMD canceller. Since the IMD canceller generates IM3($3^{rd}$-order imtermodulation) signal with $180^{\circ}$ phase difference against the IM3 of the cascode main amplifier, the IM3 power is drastically eliminated. As of the measurement results, $OP_{1dB}$, $OIP_3$, and power-add efficiency are 5.5 dBm, 15.5 dBm, and 21%, respectively. Those are 5 dB, 6 dB, and 13.5% enhanced values compared to a conventional cascode drive amplifier. The IMD3 of the drive amplifier with IMD canceller is enhanced more than 10 dB compared to that of the conventional cascode drive amplifier for input power ranges from -22 to -14 dBm.

• 한국전기전자재료학회논문지
• /
• 제27권12호
• /
• pp.792-796
• /
• 2014

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

• 센서학회지
• /
• 제18권2호
• /
• pp.128-134
• /
• 2009

Integrated circuit of a new neuron chain with a synapse function for Hodgkin-Huxley model which is a good electrical model about a real biological neuron is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Pulse type neuron chain consist of series connected current controlled single neurons through synapses. For the realization of the single neuron, a pair of voltage mode oscillators using operational transconductance amplifiers and capacitors is used. The synapse block which is a connection element between neurons consist of a voltage-current conversion circuit using current mirror. SPICE simulation results of the proposed circuit show 160 mV amplitude pulse output and propagation of the signal through synapses. Measurements of the fabricated pulse type neuron chip in condition of ${\pm}2.5\;V$ power supply are shown and compared with the simulated results.

• 한국전자파학회논문지
• /
• 제24권11호
• /
• pp.1055-1063
• /
• 2013

저 잡음 증폭기는 RF 수신단의 필수적인 요소이며, 다양한 무선시스템에서 사용하기 위하여 넓은 주파수 범위에서 동작하도록 요구된다. 전압 이득, 반사 손실, 잡음 지수, 선형성과 같은 중요한 성능지표들을 신중히 다루어서, 제안하는 LNA의 주요한 성능으로 역할을 하게끔 한다. Buffer 단에서 peaking 인덕터를 사용하며 전체적으로 cascade 구조로써 inductive shunt feedback을 LNA 입력 단에 성공적으로 적용하였다. 광대역 정합 주파수를 얻기 위한 설계식은 상대적으로 간단한 회로구성을 통해 도출된다. 입력 임피던스의 주파수 응답 분석을 위하여 pole과 zero를 광대역 응답을 실현하기 위한 특성으로 기술하였다. 입력 단에 게이트와 드레인 사이의 인덕터는 출력의 3차 고조파를 감소시킴으로 선형성을 크게 향상시킬 수 있다. 제안하는 회로를 $0.18{\mu}m$의 CMOS 공정으로 제작하였고, Pad를 포함한 광대역 LNA의 칩 면적은 $0.202mm^2$이다. 측정 결과는 1.5~13 GHz에서 입력손실은 -7 dB 이하이고, 전압 이득은 8 dB 이상이며, 잡음 지수는 6~9 dB 정도이다. 그리고 IIP3는 8 GHz에서 2.5 dBm이며, 1.8 V 전압에서 14 mA 전류를 소모한다.

• 한국전기전자재료학회논문지
• /
• 제18권3호
• /
• pp.216-218
• /
• 2005

Planar spiral inductors on silicon substrates were optimally designed using MATLAB, which is a tool to perform numerical computations with matrices. The equivalent circuit parameters of the spiral inductors were extracted from the data measured from the spiral inductors fabricated using a 0.18 $\mu\textrm{m}$ RF CMOS process. The metal width, which is a critical design parameter, was optimized for the maximum quality factor with respect to the operating frequency.