• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.05a
• /
• pp.690-692
• /
• 2009

PLL은 위상주파수검출기(PFD), 차지펌프(Charge Pump), 루프필터(Loop Filter), 전압제어발진기(VCO), Divider로 구성하고 있는데 본 논문에서는 설계된 차지펌프 PLL을 시뮬레이션을 해보고 그 결과를 정리하고 레이아웃(layout)까지 하였다. 차지펌프 설계에 있어서 전류 부정합, 전하 공유, 전하주입, 누설 전류등을 고려할 필요가 있다. 설계된 차지펌프는 전류 부정합을 감소시키기 위해 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, spurs를 억제할 수 있도록 설계되였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 specter로 시뮬레이션 하였으며, virtuso2로 레이아웃 하였다.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.5
• /
• pp.87-97
• /
• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of Korea Society of Industrial Information Systems
• /
• v.22 no.1
• /
• pp.53-59
• /
• 2017

This Paper Proposes a New High-speed Design Methodology for Delay Insensitive Asynchronous Circuits Combining with a Pseudo-NMOS Structure used for High Performance in Synchronous Circuits. Null Convention Logic(NCL) of Conventional Delay-Insensitive Asynchronous Design Methodologies has many Advantages of High Reliability, Low Power Consumption, and Easy Design Reuses not Dependant on Semiconductor Technology. However. the Conventional NCL Gates has a Complicated Stack Structure, so it Suffers from Increased Circuit Delay. Therefore, a New NCL Gates and its Pipeline Structure for High Performance, and the Proposed Methodology has been Designed and Evaluated by a $4{\times}4$ Multiplier Designed using SK-Hynix 0.18 um CMOS Technology. The Experimental Results are Compared with a Conventional NCL in Terms of Power and Delay and shows that the Propagation Delay of the Proposed Multiplier is Reduced by 85% Compared with the Conventional NCL Multiplier.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.861-862
• /
• 2015

In this paper we present a low area 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is fabricated using Magnachip/SK Hynix 1-Poly 6-Metal $0.18-{\mu}m$ CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit showed improved power dissipation of 1.9mW, and chip area of $0.45mm^2$ as compared to conventional research results at the power supply of 1.8V. The designed circuit also showed high SNDR (Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.755-758
• /
• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.271-274
• /
• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.16 no.4
• /
• pp.33-41
• /
• 2006

RSA cryptosystem is of great use in systems such as IC card, mobile system, WPKI, electronic cash, SET, SSL and so on. RSA is performed through modular exponentiation. It is well known that the Montgomery multiplier is efficient in general. The critical path delay of the Montgomery multiplier depends on an addition of three operands, the problem that is taken over carry-propagation makes big influence at an efficiency of Montgomery Multiplier. Recently, the use of the Carry Save Adder(CSA) which has no carry propagation has worked McIvor et al. proposed a couple of Montgomery multiplication for an ideal exponentiation, the one and the other are made of 3 steps and 2 steps of CSA respectively. The latter one is more efficient than the first one in terms of the time complexity. In this paper, for faster operation than the latter one we use binary signed-digit(SD) number system which has no carry-propagation. We propose a new redundant binary adder(RBA) that performs the addition between two binary SD numbers and apply to Montgomery multiplier. Instead of the binary SD addition rule using in existing RBAs, we propose a new addition rule. And, we construct and simulate to the proposed adder using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is faster by a minimum 12.46% in terms of the time complexity than McIvor's 2 method and existing RBAs.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.9
• /
• pp.183-195
• /
• 2012

We propose a variable-latency Decimal Floating Point(DFP) adder which adopts the dual data path scheme. It is to speed addition and subtraction of operand that has identical exponents. The proposed DFP adder makes use of L. K. Wang's operand alignment algorithm, but operates through high speed data-path in guaranteed accuracy range. Synthesis results show that the area of the proposed DFP adder is increased by 8.26% compared to the L. K. Wang's DFP adder, though critical path delay is reduced by 10.54%. It also operates at 13.65% reduced path than critical path in case of an operation which has two DFP operands with identical exponents. We prove that the proposed DFP adder shows higher efficiency than L. K. Wang's DFP adder when the ratio of identical exponents is larger than 2%.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.303-317
• /
• 2013

Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.