• ETRI Journal
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• v.28 no.1
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• pp.115-118
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• 2006

In this letter, a simple model parameter extraction methodology for an on-chip spiral inductor is proposed based on a wide-band inductor model that incorporates parallel inductance and resistance to model skin and proximity effects, and capacitance to model the decrease in series resistance above the frequency near the peak quality factor. The wide-band inductor model does not require any frequency dependent elements, and model parameters can be extracted directly from the measured data with some curve fitting. The validity of the proposed model and parameter extraction methodology are verified with various size inductors fabricated using $0.18\;{\mu}m$ CMOS technology.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.235-240
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• 2007

A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.815-817
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• 2012

본 논문에서는 차량 충돌 예방 레이더 시스템-온-칩용 77GHz 고주파 전단부(RF front-end)를 제안한다. 이러한 고주파 전단부는 77GHz의 동작주파수를 가진 저 잡음 증폭기와 고주파 전력 증폭기로 구성된다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 저잡음 증폭기의 경우 전압이득이 36dB로 최근 발표된 연구결과 중 가장 우수한 수치를 보였다. 전력 증폭기는 포화전력과 출력 $P_{1dB}$이 18dBm과 15dBm으로 기존 연구결과 중 가장 우수한 결과를 각각 보였다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.983-984
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• 2006

Multi-band VCO with fast response adaptive frequency calibration (AFC) technique is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators for 802.11a/b/g WLAN applications. To linearize its frequency-voltage gain, optimized multiple MOS varactor biasing technique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched-capacitor bank is used and a wide-range digital logic quadricorrelator is implemented for fast frequency detector.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• Journal of information and communication convergence engineering
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• v.9 no.1
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• pp.11-15
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• 2011

A Differential line inductor is proposed for a differential power amplifier. The proposed differential line inductor is composed of two conventional line inductors rearranged to make the current direction of the two line inductors identical. The proposed line inductor is simulated with a 2.5-D and a 3-D EM simulator to verify its feasibility with the substrate information in a 0.18-${\mu}m$ RF CMOS process. The inductances of various line inductors implemented with printed circuit boards were measured. The feasibility of the proposed line inductor was successfully demonstrated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.185-187
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• 2017

국제 표준화 기구인 ISO/IEC와 NIST(National Institute of Standards and Technology)에서는 정보 유출 방지 및 정보의 유효성 인증을 위해 다양한 암호 기법들을 표준으로 권고하고 있다. 그 중 NIST SP 800-38D에서 표준으로 권고된 GCM(Galois/Counter Mode) 인증 암호화 모드는 블록암호의 CTR 운영모드와 GHASH를 이용하여 메시지의 기밀성과 무결성을 동시에 제공하는 운영모드이다. 본 논문에서는 ARIA 블록암호 기반의 ARIA-GCM 프로세서를 Verilog HDL로 모델링 하고, Virtex5 FPGA로 구현하여 정상 동작함을 확인하였다. $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 20 MHz의 동작주파수에서 44,986 GE로 구현되었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.151-153
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• 2016

80/128-비트 마스터키 길이와 ECB, CBC, OFB, CTR의 4가지 운영모드를 지원하는 PRESENT 경량 블록암호 프로세서를 설계하고, Virtex5 FPGA에 구현하여 정상 동작함을 확인하였다. PRESENT 크립토 프로세서를 $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 8,237 GE로 구현되었으며, 최대 434 MHz 클록으로 동작하여 868 Mbps의 성능을 갖는 것으로 예측되었다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.4
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• pp.176-181
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• 2001

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.