• ETRI Journal
• /
• v.44 no.5
• /
• pp.826-836
• /
• 2022

Signal decomposition is a computational technique that dissects a signal into its constituent components, providing supplementary information. In this study, the capability of two common signal decomposition techniques, including wavelet-based and empirical mode decomposition, on preterm birth classification was investigated. Ten time-domain features were extracted from the constituent components of electrohysterogram (EHG) signals, including EHG subbands and EHG intrinsic mode functions, and employed for preterm birth classification. Preterm birth classification and anticipation are crucial tasks that can help reduce preterm birth complications. The computational results show that the preterm birth classification obtained using wavelet-based decomposition is superior. This, therefore, implies that EHG subbands decomposed through wavelet-based decomposition provide more applicable information for preterm birth classification. Furthermore, an accuracy of 0.9776 and a specificity of 0.9978, the best performance on preterm birth classification among state-of-the-art signal processing techniques, were obtained using the time-domain features of EHG subbands.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.4
• /
• pp.917-922
• /
• 2010

In this paper, a new temperature-insensitive CMOS dual-mode current reference for low-voltage low-power mixed-mode circuits is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature(PTAT) current and a complementary to absolute temperature(CTAT) current. The temperature insensitivity was achieved by the mobility and the other which is inversely proportional to mobility. As the results, the temperature dependency of output currents was measured to be $0.38{\mu}A/^{\circ}C$ and $0.39{\mu}A/^{\circ}C$, respectively. And also, the power dissipation is 0.84mW on 2V voltage supply. These results are verified by the $0.18{\mu}m$ n-well CMOS parameter.

• Korean Journal of Optics and Photonics
• /
• v.19 no.5
• /
• pp.343-348
• /
• 2008

This study was carried out to commercialize FTTH by developing a burst mode optical receiver for E-PON. The optical receiver was manufactured by minimizing the capacitance of a photodiode to improve sensitivity for meeting 10, 20 km OLT Rx standard of E-PON at the transmission speed of 1.25 Gb/s. When bit-error ratio is $10^{-12}$ and PRBS is $2^5-1$, sensitivity is -26 dBm, loud/soft ratio is 23 dB. Both preamble time and guard time were set to 102.4 ns (128 bit). After comparing a photodiode whose capacitance is 0.53 pF with another photodiode whose capacitance has been minimized to 0.26 pF, we could see that sensitivity improved to 0.7 dBm and so did bandwidth to 190 MHz of burst mode for the optical receiver manufactured by the photodiode whose capacitance is 0.26 pF.

• Journal of IKEEE
• /
• v.4 no.2 s.7
• /
• pp.181-191
• /
• 2000

In this paper, two schemes of generating reference voltages using enhancement-mode MOS transistors and resistors are proposed. The first one is a voltage-mode scheme where the temperature compensation is made by summing a voltage component proportional to a threshold voltage and a voltage component proportional to a thermal voltage. In the second one, that is a current-mode scheme, the temperature compensation is made by summing a current component proportional to a threshold voltage and a current component proportional to a thermal voltage. The designed circuits have been simulated using a $0.65{\mu}m$ n-well CMOS process parameters. The voltage-mode circuit has a temperature coefficient less than $48.0ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.21%/V for a temperature range of $-30^{\circ}C{\sim}130^{\circ}C$ and a VDD range of $3V{\sim}12V$. The current-mode circuit has a temperature coefficient less than $38.2ppm/^{\circ}C$ and a VDD coefficient less than 0.8%/V for $-30^{\circ}C{\sim}130^{\circ}C\;and\; 4V{\sim}12V$. The power consumption of the voltage-mode and current-mode circuits are $27{\mu}W\;and\;65{\mu}W$ respectively for 5V and $30^{\circ}C$. Measurement results show that the voltage-mode reference circuit has a VDD coefficient less than 0.63%/V for $30^{\circ}C{\sim}100^{\circ}C$ and has a temperature coefficient less than $490ppm/^{\circ}C\;for\;3V{\sim}6V$. The proposed reference circuits are simple and thus easy to design. The proposed current-mode reference circuit can be designed to generate a wide range of reference voltages.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.10 no.4
• /
• pp.149-157
• /
• 2002

This paper is to investigate collapse mechanisms of CFRP(Carbon Fiber Reinforced Plastics)composite tubes and to evaluate collapse characteristics on the change of interlaiminar number and ply orientation angle of outer under static and impact axial compression loads. When a CFRP composite tube is crushed, static/impact energy is consumed by friction between the loading plate and the splayed fronds of the tube, by fracture of the fibers, matrix and their interface. These are associated with the energy absorption capability. In general, CFRP tube with 6 interlaminar number(C-type), absorbed more energy than other tubes(A, B, D-types). The maximum collapse load seemed to increase as the interlaminar number of such tubes increases. The collapse mode depended upon orientation angle of outer of CFRP tubes and loading status(static/impact). Typical collapse modes of CFRP tubes are wedge collapse mode, splaying collapse mode and fragmentation collapse mode. The wedge collapse mode was shown in case of CFRP tubes with 0° orientation angle of outer under static and impact loadings. The splaying collapse mode was shown in only case of CFRP tubes with 90°orientation angle of outer under static loadings, however in Impact tests those were collapsed in fragmentation mode .

• Korean Journal of Agricultural Science
• /
• v.40 no.4
• /
• pp.347-351
• /
• 2013

This study was conducted to estimate the effect of sex, breed and on the basis of the records on 300 pigs of Duroc, Landrace and Yorkshire breeds raised at the National Institute of Animal Science. Yorkshire was observed to be superior to other breeds between 90 to 110 kg of body weight. Thicker backfat was estimated in the B-mode than in A-mode of 110 kgs range than in 90 kgs. Loin eye muscle area was larger in the final weight of 110kg than in 90 and the Duroc had significantly (p<0.05) larger loin eye muscle area than other breeds. Thinner backfat was observed in males than in females in both modes of backfat measurements and in both of the final weights of test. Females had significantly larger loin eye muscle area than males, and the difference between the two sexes were larger in the final weight of 110 kg than in 90 kg. Analysis models concluded that backfat thickness certainly influences the body weight gain when at 90 kgs and 110 kgs analysed with A-mode and B-mode respectively.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.10 no.12
• /
• pp.3614-3621
• /
• 2009

In this paper, A CMOS low-voltage current mode integrator is designed. The designed current-mode integrator is based on linear cascode circuit that is newly proposed in this paper. When it is compared with gain(43.7dB) and unity gain frequency(15.2MHz) of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain(47.8dB) and unity gain frequency(27.8MHz). And a 5th Chebyshev current-mode filter with 7.03MHz cutoff frequency is designed. The designed all circuits are simulated by HSPICE using 1.8V-$0.18{\mu}m$ CMOS technology.

• Journal of IKEEE
• /
• v.15 no.2
• /
• pp.134-142
• /
• 2011

This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.

• The Journal of the Korea Contents Association
• /
• v.16 no.10
• /
• pp.291-298
• /
• 2016

The aim of the study was to investigate the diagnostic value of the color Doppler twinkling artifact in disease of urinary system. The intensity of twinkling artifact(TA) with color Doppler was classified into 3 levels, 0(non-TA) to 3(distinct TA). In the in vitro study, acorn jelly with various materials on top was examined using color Doppler at B-mode sonography in a water bath for TA. 31 patients with diagnosis of urinary calculi(renal stones 16, urinary stones 15) based on B-mode sonography were studied in vivo for TA. The materials with rough surfaces such as salt, screw and cubics at B-mode sonography with color Doppler contributed to causing TA. At B-mode sonography without color Doppler 37% of renal stones and 60% of ureter stones were detected. but at B-mode sonography with color Doppler TA was demonstrated for all cases. Superficial roughness of materials affected occurrence of TA at B-mode sonography with color Doppler. Therefore, TA at B-mode sonography without color Doppler could play a role in confident diagnosis of the disease of urinary system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.411-414
• /
• 2011

This paper describes a tripple-mode DC-DC buck converter with DPSS Fucntion. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(80mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~80mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 97.02% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is $1465um{\times}895um$ including pads.