• KEPCO Journal on Electric Power and Energy
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• v.2 no.4
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• pp.577-582
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• 2016

This Study focused on the development of SMPS (Switching Mode Power Supply) to supply the constant votage and current nevertheless LED fluorescent Light generated the electric noise (with Harmonics) and Inrush current at instant time of turn-on and off. Recently, according to the Green policy in government, the LED fluorescent Lighter showed the rapidly increasing tend as indoor and outdoor Lighter. But, because of costs, LED fluorescent Light not considered and neglected the following items; power factor, efficiency, Harmonics and Inrush current. So, we are developed the SMPS about 3 key issues as follows: 1st, power factor and efficiency is 85%. 2nd, the switching noisy by harmonic is minimized. 3rd, the Inrush current at turn on and off time is reduced the minimum 0.3 A after $100{\mu}sec$ on turnon time. The proposed SMPS adjusted by LNK 409 driver (included the high frequency modulation function). Although, the developed SMPS maintained the about 85% of power factor and efficiency. but, the SMPS must be generated low heat by the variation of minute load current at switching timing. To improve the above weak point, the developed SMPS have the feedback monitoring circuit between input side and output side to maintain the power factor and efficiency. Also, we are studied the time-constant of control circuit to output the constant voltage and current nevertheless the load disturbance of LED lighting. The LED fluorescent Light of 46W is checked the above items.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.869-872
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• 2005

This paper presents a new switchable dual mode VCO(Voltage-Controlled Oscillator). The VCO is efficient in dual mode operation and has self-bias adjustment based on the operation frequencies of 2.4 GHz and 5 GHz. The switching is done using MOS transistors and tuning is done using MOS varactors. It is implemented using TSMC 0.18${\mu}$m CMOS technology. It is powered by 1.8V supply. The measured results showed that the overall tuning range is approximately 13% at 5 GHz and 8% at 2.4 GHz. The measured phase noise is approximately -102 dBc/Hz at 1 MHz offset for 5 GHz and -89 dBc/Hz at 600kHz offset for 2.4 GHz. The VCO showed tail currents of 2mA in 5GHz mode and 2.5mA in 2.4GHz mode from a 1.8 V supply, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2378-2390
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• 1997

We, in this paper, have implemented E1 HDSL(high-bit-rate digital subscriber line) function over an ATM switching system. The maximum loop lengths for subscriber service and cell loss rates to meet the bit error rate of $10^{-7}$ at transmission of 2B1Q HDSL data of E1 rate over existing telephone copper wires in the presense of the significant impairments such as crosstalk, impulse noise, power line noise and longitudinal over the CSAs environment consisting of 26 gauge and 24 gauge unloaded copper telephone lines has assessed. We have confirmed the typical media services function such as video on demand(VOD) service for MPEG-1, image conference service and high-speed Internet access service over ATM switching system.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.12
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• pp.639-647
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• 2001

We present an integrated optical microswitch, composed of silicon waveguides, gold-coaled silicon micromirrors, and electrostatic contact actuators, for applications to the optical signal transceivers. For a low switching voltage, we modify the conventional curled electrode microactuator into a electrostatic microactuator with touch-down beams. We fabricate the silicon waveguides and the electrostatically actuated micromirrors using the ICP etching process of SOI wafers. We observe the single mode wave propagation through the silicon waveguide with the measured micromirror loss of $4.18\pm0.25dB$. We analyze major source of the micromirror loss, thereby presenting guidelines for low-loss micromirror designs. From the fabricated microswitch, we measure the switching voltage of 31.74V at the resonant frequency of 6.89kHz. Compared to the conventional microactuator, the present contact microactuator achieves 77.4% reduction of the switching voltage. We also discuss a feasible method to reduce the switching voltage to 10V level by using the electrode insulation layers having the residual stress less than 30MPa.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.91-98
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• 1999

An integrated ZCS quasi-resonant converter(QRC) for the power factor correction with a single switch is presented in this paper. The power factor correction can be achieved by the discontinuous conduction mode(DCM) operation of the input current. The proposed converter gives the good power factor, low line current harmonics, and tight output regulation. The input current waveform of the prototype designed using design equations shows about 15% of total harmonic distortion at rated condition. Also, the efficiency and power factor can be obtained about 86% and 0.985, respectively, at rated condition. The proposed converter is suitable for a low power level converter with a tightly regulated low output voltage and switching frequency of more than several hundreds kHz.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.1-7
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• 2016

In this paper, the tunable filter based on high power cavity using mechanical switch for 1.5 GHz band is presented. The LPF is inserted to eliminate the spurious wave, coupler is embeded to extract the output power, and then the tunable filter system is configured using mechanical switch. The LPF obtains attenuation over 40 dB between 4 GHz and 12.75 GHz, Coupler is satisfied with coupling value 40 dB and coupling isolation over 55 dB. The tunable filter system using mechanical switch obtains insertion loss 0.88 dB at bypass mode between 1,495.9 MHz and 1,510. 9 MHz, 3.29 dB at fil mode between 1,495.9 MHz and 1,500.9 MHz. It is also satisfied with output power of 132 W at the center frequency 1,498.4 MHz, and switching time below 10 ms.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.