• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Korean Journal of Optics and Photonics
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• v.11 no.2
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• pp.108-113
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• 2000

This paper presents a simple but novel gain deviation detector scheme which can be used for general gain-clamping systems. By using the difference of ASEJprobe powers extracted from the edges of gain-flattened bandwidth, gain deviation of EDFA can be exactly detected regardless of the operating condition of a constructed EDFA. To prove the vahd1ty of the suggested scheme, we Implemented gain clamping systems on a single EDFA and cascaded EDFA's link and achieved sufficient gam-clamping performance without the elaborate measurement for tlIe determination of control parameters. eters.

• Journal of Engineering Education Research
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• v.5 no.1
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• pp.19-26
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• 2002

This paper presents a virtual laboratory system which can be creating efficiencies in the learning process. The proposed virtual laboratory system for electrical circuits provides interactive learning environment under which the multimedia capabilities of world-wide web can be enhanced. The virtual laboratory system is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. In the proposed virtual laboratory system, every activity occurred in the virtual laboratory will be recorded on database and printed it out on the preliminary report form. The database connectivity is made by PHP and the virtual laboratory environment is set up slightly differently for each learner The virtual laboratory system is composed of four important components : Principle classroom, Simulation classroom, Virtual experiment classroom and Management system. Learning efficiencies as well as faculty productivity are increased in this innovative teaching and learning environment.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.6-12
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• 1984

The basic binary quantized first-order digital phase locked loop (DPLL) is modified in order to reduce the aquisition time and steadyftate phase error. Adding the loop that corrects the phase difference by detecting the falling zero-crossing time, an effort for the improving the performance is performed and the performance compared with that of the basic DPLL. Using a graphical method, the phase locking processes of the modified DPLL for a phase step and a frequency step input are depicted visually in the absence of noise. The performance of the modified DPLL for a sinusoidal input added narrow band random noise is evaluated using the Chapman-Kolmogorov equation. This approach is verified by direct computer simulation. The steady-state phase error and the average aquisition time of the modified DPLL are compared with those of the basic DPLL, It is shown that the aquisition time of the modified DPLL is shortened about twice, also, as signal to noise ratio increases, the effect of the modification increases and the steady-state phase error approaches to zero.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.1 no.2
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• pp.49-56
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• 1987

To save energy consumption, it is proposed to operate a discharge lamp with high frequency power. When designing a high frequency operating circuit containing a discharge lamp, the character of a lamp may be needed. And there are various methods to get and models for this. In this study, to present the volt-ampere character of a fluorescent lamp which gives a good saving effect, the nonlinear resistance model is suggested. And the validity of the model is verified by applying the model for the circuits with inductor ballast and capacifor ballast. This model, in contrast with the others, can be easily obtainable. And for comparison, the model using a modified Francis equation is examined. The method used in this study can be basically applied to the other discharge lamps. As a result, 1) Approximated 3rd order polynomial of nonlinear resistance model gives a good simulation result. 2) When operating in high frequency, the model using a modified Francis equation with constant coefficients can't be applied.

• Korean Journal of Cognitive Science
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• v.7 no.3
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• pp.37-60
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• 1996

From the biopsychological point of view,learning could be defined as the processes to transfer the information that we obtain from environment to the neural circuits in the brain.In the studies to determine the biological substrates of learning and memory,there was a remarkable effort to identify neural circuits related with a specific type of learning and to describe the mechanixm of neural plasticity of learning and memory,under the assumption that the memory orinformation may be stored as a modificationof neural synapes in the central nerviys system.On the other hand,there was a different kind of tendency to analyze the mechanism of interactions between neural substrates involved in learning and memory,under the assumption that a specific information may be represented in the patterns of comples neural network of the central nervous system.The present review,in the former position.focused on the research methods and the chracteristics and finding of the investigations employing animal model systems to indentify the essential site of engram for learning and memory.Specifically,the review presents major advances in ourunderstanding of the memory trace circuit for a specific type of learning,with the use of animal model system,the detemination of the critical lodi of neuaral plastic chabges In learing abd memory,and the neurophysiological an biocemical mechanixms of the neural modifia by learint.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.173-180
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• 2022

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.23-32
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• 2006

Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1656-1666
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• 1999

The more complex and large digital circuits become, the more important delay test becomes which guarantees that circuits operate in time. In this paper, the proposed algorithm is developed, which enable the fast indirect implication for efficient test pattern generation in sequential circuits of standard scan environment. Static learning algorithm enables application of a new implication value using contrapositive proposition. The static learning procedure found structurally, analyzes the gate structure in the preprocessing phase and store the information of learning occurrence so that it can be used in the test pattern generation procedure if it satisfies the implication condition. If there exists a signal line which include all paths from some particular primary inputs, it is a partitioning point. If paths passing that point have the same partial path from primary input to the signal or from the signal to primary output, they will need the same primary input values which separated by the partitioning point. In this paper test pattern generation can be more effective by using this partitioning technique. Finally, an efficient delay fault test pattern generator using indirect implication is developed and the effectiveness of these algorithms is demonstrated by experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.95-101
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• 2008

We have used diversely the multilayer ceramic oscillator of the SMD(Surface Mounted Device) package technology that connects the crystal with the chip package. Such an oscillator occurs a stray inductance and a parasitic capacitance by the length and inner pattern. And it has been happened an amplitude attenuation and signal loss due to the reflection of power source and noise component. So we don't evaluate the precise performance of the oscillator for these factors. In this paper we have developed the Jig system to evaluate the performance of the oscillator. Through this system, we will expect an advanced performance of the oscillator and redesign an oscillator of the low jitter characteristics and low phase noise.