Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Development of Jig Circuit for Performance Evaluation of an Oscillator

발진기의 성능평가를 위한 지그 회로의 개발

  • Lin, Chi-Ho (School of Computer Science, Semyung University) ;
  • Yoon, Dal-Hwan (Department of Electronic Engineering, Semyung University)
  • Published : 2008.11.25
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Abstract

We have used diversely the multilayer ceramic oscillator of the SMD(Surface Mounted Device) package technology that connects the crystal with the chip package. Such an oscillator occurs a stray inductance and a parasitic capacitance by the length and inner pattern. And it has been happened an amplitude attenuation and signal loss due to the reflection of power source and noise component. So we don't evaluate the precise performance of the oscillator for these factors. In this paper we have developed the Jig system to evaluate the performance of the oscillator. Through this system, we will expect an advanced performance of the oscillator and redesign an oscillator of the low jitter characteristics and low phase noise.

최근 발진수정자에 칩패키지를 결선한 SMD형의 적층세라믹 발진기를 많이 사용한다. 이러한 발진기들은 그 길이 및 패키지 내부의 패턴 등에 의하여 부유인덕턴스 및 기생 커패시턴스가 발생하고, 전원의 반사 및 잡음 발생으로 출력신호의 진폭감소 및 신호 손실이 발생하여 발진기 성능을 정상적으로 평가할 수 없다. 본 논문에서는 발진기와 계측기의 부정합임피던스로 부터 발생한 신호 손실 및 진폭감소를 방지하기 위해 지그 회로를 개발한다. 이를 통하여 발진기의 정확한 스펙트럼 분석 및 성능을 평가함으로써 발진기의 성능향상을 기한다.

Keywords

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