• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.969-973
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• 1995

In this paper, a new parallel Multiplier array is proposed to reduce the multiplication time by modifying CAS(carry select adder) cell structure used in the conventional parallel multiplier array. It is named MCSA(modified CSA) that assignes the addend and augend to the inputs of CSA faster than Ci(carry input). Also the designed DCSA (doubled inverted input CSA) is appended after the last product term for the carry propagation adder. The proposed scheme is designed with MCSA and DCSA, and simulated. It is verified that the circuit size is increased about 13% compared with the conventional multiplier array with CSA cell but the operation time is reduced about 52%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2081-2093
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• 1994

In this study, we design and implement 64 QAM demodulator which has 155 Mbps, first level of CCITT G707 SDH(Synchronous Digital Hierachy) for STM 1 signal transmission. Carrier recovery which effects the demodulator performance uses decision feedback carrier using 8 bits A/D converter. Also, PSF(Pulse Shaping Filter) is 7 order elliptic filter. Carrier recovery circuit is designed and implemented digital type which use high 3 bits of 8 bits conversion data as data and the order low bits as error data and hybrid type which use VCO and analog integrator. Therefore we obtain stable performance recovery.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.95-100
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• 2006

In this paper, we designed amplitude equalizer which is composed of amplifier, complementary shaping filter and attenuator in order to improve flatness of high order bandpass filter. We modified Chebyshev polynomial and calculated the prototype elements for complementary shaping filters by network synthesis. The amplitude equalizer is realized that it connects the 4th order complementary shaping filter designed by using calculated the prototype elements to the amplifier compensating for insertion loss and improving return loss, and with the attenuator for gain control. Using proposed amplitude equalizer, We certificated improvement in flatness of 13th order bandpass filter at WiBro band.

• 한국정보통신설비학회:학술대회논문집
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• 2003.08a
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• pp.81-84
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• 2003

부분방전시험은 고전압 고정자 권선의 절연상태를 검사, 평가 할 수 있는 중요한 수단이다. 전동기와 발전기에서 일어나는 절연 악화의 징후로써 부분방전이 발생되며 이러한 부분방전 신호를 검출하기 위한 센서로 SSC(Stator Slot Couple)를 사용한다. 하지만 현재 사용되고 있는 대부분의 SSC의 경우 설계에 있어 특성 임피던스가 실제구조에서 정확히 고려되지 않는 경향이 있다. 실제로 고정자 슬롯에 부착된 마이크로스트립 센서의 특성 임피던스는 정확히 50옴으로 정합 되지 않으며 이것은 센서의 성능에 중요한 영향을 미치게 된다. 그러므로 본 논문에서는 부분방전 센서의 성능을 개선시키기 위해 결합 전송선로(Coupled transmission line)를 이용한 임피던스 정합회로를 제안하고자 한다. 제안된 센서의 성능을 입증하기 위하여 고정자 슬롯에 설치된 기존의 SSC와 임피던스 정합회로를 부착한 센서를 시뮬레이션 한 후 비교 분석하였다. 결과적으로 제안된 정합 회로는 광대역 임피던스 정합 특성을 가지며 임피던스 부정합때문에 일어나는 기존 SSC의 성능 악화를 개선할 수 있었다.

• The Journal of Korean Association of Computer Education
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• v.10 no.4
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• pp.17-25
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• 2007

In this paper, the simplification procedure of Karnaugh Map, which is essential to design digital logic circuits, was implemented as a web-based educational tool by Java applet. The learners can make virtual experiments on the simplification of the digital logic circuit by clicking on some buttons or filling out some text fields. The proposed simplification procedure was implemented as a Java applet which is based on the Modified Quine-McCluskey algorithm. Thus, the implemented Java applet will enable the learners to enhance the learning efficiency as a auxiliary educational tool.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.72-83
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• 2002

In this paper, a novel low-power VLSI system architecture was proposed. By exploiting software control of supply voltages, it simplifies hardware implementation, reduces power consumption efficiently, and avoids complicated interface circuits. The proposed architecture models clock frequency-supply voltage relationship by software modelling, enables individual control of supply voltages for all chips in the system, and restricts clock frequency to discrete levels of $f_{CLK}$, $f_{CLK}$2, $f_{CLK}$3... where $f_{CLK}$ is the master clock frequency A prototype system was implemented by modifying off-the-shelf microprocessor evaluation board and adding simple discrete devices such as level shifters and voltage switches. It was measured that the power consumption was reduced from 0.58W to 0.12W in the Prototype system. system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.715-722
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• 2000

In this paper, the PLDRO is designed and implemented for X-band. It is comprised of tunable high Q resonator with a varactor diode for frequency tuning, loop filter and a 1/8 prescaler which up to 10GHz. Also, it is implemented a TCXO and a VCO signal into the phase detector and achieved a highly stable signal source. From the measurement, the designed PLDRO has the output power of 2.5dBm at 8GHz and phase noise of -64.33dBc at 10KHz offset from carrier. Its characteristic is 26 dBc. This PLDRO has much better temperature stability.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1170-1175
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• 2003

In this paper, the output power improvement of Push-Push FET DRO by adding the identical DR at the drain port as one used in the gate port, has been theoretically investigated. The investigation shows that the DR located between two microstrip lines locks the phase difference of two FET's outputs at 180 degree and improves the output power of Push-Push FET DRO. Since this effect can be used for correcting the impedance difference between two FETs output circuits and the electrical length error of the power combiner at the output circuit of Push-Push DRO, which may occur when fabricate the oscillator, the oscillator with an additional DR can be useful structure for fabricating oscillator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1313-1323
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• 1991

n this thesis CAM(content Addressable Memory) generator and graphic display tool for run-plot sequence in automatic generation of CAM are presented. We show that implementing the layout generation, graphic menu, mouse driver, and data structure by using the basic classes is clear and easy in modification than the conventional procedural language. For the implementation of generator which is independent of design rule or process, we use the parameterized cell so that basic cell can be changed according to user's inputs. and perform the layout by means of placement and routing using pitch mathching. Finally, the display of CIF which generated and constitution of graphic menu for total run-plot sequence are explained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.