• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.9
• /
• pp.875-880
• /
• 2011

We design and analyze the cloaking circuit using 2D transmission line structure to make up for the weakness of the established cloaking circuit using only lumped inductor and capacitor elements. The 2D transmission line structure enables one to conveniently design the cloaking circuit with available element values. All the necessary analysis and synthesis(design) formulas have been derived. A cloaking circuit for a cylindrical scatterer in free space has been designed based on the provided design formulas and its effects have been investigated using the circuit simulator ADS. The effect of the cloaking medium for this specific case has been observed to be about 10.5 dB.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.385-392
• /
• 2013

In this paper, microstrip antenna to enhance the isolation between transmitting port and receiving port under the proximity objects is proposed, and applied to the Doppler radar sensor working at 5.8GHz ISM band which detects vital signals of a human body. Two 3dB quadrature hybrids are placed around radiation patch to form a balanced structure between transmitting port and receiving port, such that it consistently provides enhanced Tx/Rx isolation and excellent return loss over nearby objects. It is theoretically analyzed and simulated to verify the validity of the proposed application. The fabricated antenna that is 2mm away from the human body, has more than 16 dB return loss and at least 30dB isolation over ISM frequency band of 5.8GHz.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.1
• /
• pp.73-77
• /
• 2007

In this paper, we propose a VLSI architecture of an LMS filter based on a Cyclo-static scheduler for fast computation of LMS filteing algorithm which is widely used in adptive filtering area. This process is composed of two steps: scheduling and circuit synthesis. The scheduling step accepts a fully specified flow graph(FSFG) as an input, and generates an optimal Cyclo-static schedule in the sense of the sampling rate, the number of processors, and the input-output delay. Then the generated schedule is transformed so that the number of communication edges between the processors. The circuit synthesis part translates the modified schedule into a complete circuit diagram by performing resource allocations. The VLSI layout generation can be performed easily by an existing silicon compiler.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.1 s.116
• /
• pp.90-95
• /
• 2007

Chaotic OOK(On-Off Keying) modulation method can be used in LDR(Low Data Rate) UWB systems. The chaotic generator in one of the most important circuit in this system. The traditional chaotic generator circuits using analog feed back technique have low yield characteristic due to the process variation. A novel quasi-chaotic signal generator using digital PN-sequence in proposed in this paper and verified in 0.18um CMOS teleology.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.11
• /
• pp.30-36
• /
• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.12
• /
• pp.48-54
• /
• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.2
• /
• pp.85-96
• /
• 2017

In this paper, a 2~18 GHz wideband 6-port network is designed and fabricated to extend the measurement frequency bandwidth of noise parameter measurement method using 6-port network. In order to design a broadband 6-port network, a wilkinson power divider and a directional coupler with wideband characteristics are designed. The wilkinson power divider is designed as a three-section structure to achieve wideband characteristics. The direction coupler is designed as a three-section structure and slot-coupled structure using multi-layer substrate to obtain wideband characteristics. A wideband 6-port network is designed and fabricated combining the designed power divider and coupler. The measured results of the fabricated 6-port network for the 2~18 GHz band show characteristics applicable to the noise parameter measurement method.

• The Journal of the Korea Contents Association
• /
• v.7 no.2
• /
• pp.92-99
• /
• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Journal of the Korean Society for Railway
• /
• v.19 no.3
• /
• pp.297-303
• /
• 2016

This paper introduces auxiliary power supply systems (APS) for railroad applications and proposes a new power conversion structure for highly-efficient and lightweight APS systems. The proposed structure focuses on an improvement of the power density in APS. It eliminates unnecessary power conversion stages in the conventional APS structure by modulating the dc/dc converter circuit and the structure of the system. The dc/dc converter circuit used in the proposed structure is based on a multi-level half-bridge converter, a widely used topology in railroad APS applications; a flying capacitor is newly added to the conventional circuit. The added capacitor is used not only to enhance the soft switching condition of the switches, but also so that the new pantograph will have a side voltage source of a battery charger in the APS structure. Since the battery charger uses the pantograph side voltage source in the proposed structure, rather than using the output of the main dc/dc converter in the conventional structure, the size and efficiency of the main dc/dc converter are reduced and increased, respectively. To verify the effectiveness of the proposed structure, simulation results will be presented with metropolitan transit APS specifications.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.1
• /
• pp.13-22
• /
• 2001

This paper presents three dimensional structure of RF packages and the improvement effect of its electrical characteristics when implementing RF transceivers. We divided RF modules into several subunits following each subunit function based on the partitioning algorithm which suggests a method of three dimension stacking interconnection, PAA(pad area array) interconnection and stacking of three dimensional RF package structures. 224MHz ITS(Intelligent Transportation System) RF module subdivided into subunits of functional blocks of a receiver(RX), a transmitter(TX), a phase locked loop(PLL) and power(PWR) unit, simultaneously meeting the requirements of impedance characteristic and system stability. Each sub­functional unit has its own frequency region of 224MHz, 21.4MHz, and 450KHz~DC. The signal gain of receiver and transmitter unit showed 18.9㏈, 23.9㏈. PLL and PWR modules also provided stable phase locking, constant voltages which agree with design specifications and maximize their characteristics. The RF module of three dimension stacking structure showed $48cm^3$, 76.9％ reduction in volume and 4.8cm, 28.4％ in net length, 41.8$^{\circ}C$, 37% in maximum operating temperature, respectively. We have found that three dimensional PAA package structure is able to produce high speed, high density, low power characteristics and to improve its functional characteristics by subdividing RF modules according to the subunit function and the operating frequency, and the features of physical volume, electrical characteristics, and thermal conditions compared to two dimensional RF circuit modules.