• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.93.1-93.1
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• 2015

근래 디스플레이 분야에서 OLED가 시장을 주도하면서 이 공정에 가장 적합한 진공펌프로 크라이오 펌프가 주목을 받고 있다. 화소 형성 공정에 사용되는 유기물이 수분에 취약하기 때문인데, 크라이오 펌프가운데서 특별히 수분만 집중적으로 배기할 수 있는 워터펌프(CWP or cold trap)가 각광받고 있다. 이에 HM GVT는 중소기업청 중소기업개발지원사업의 일환으로 진행된 2014년도 구매조건부 신제품 개발사업에 선정되어 '극저온 G-M냉동기를 이용한 대용량 Cold Trap개발' 과제를 수행하면서 32인치 급으로 수분에 대해서 30,000 [L/s] 이상의 배기속도를 가지는 대형 CWP를 개발하고 있다(수요처: (주)아바코). 통상적으로 흡기구가 30인치라면 수분 배기속도는 대략 65,000 L/s에 이르고 200 W 냉각능력이면 최대 수분 분압 0.008 mbar에서 작동시킬 수 있다. 따라서 1차년도의 목표는 큰 배기용량과 대형 사이즈의 CWP를 개발하기 위해 80 K에서 200 W 이상의 냉동능력을 보유한 단단 G-M 극저온냉동기를 선행 개발하는 것이다. 이에 현재 최대 냉동능력 80 K에 130 W의 냉동능력을 가지는 HPS055모델을 이용하여 다양한 예비시험들을 수행하여 최적의 설계인자들을 도출하였고 이를 근거로 80 K에서 200 W 이상의 냉동능력을 가지는 HPS80200모델을 설계 및 제작, 성능시험을 수행하였다. 이에 국내 최초로 80 K에서 200 W의 냉동능력을 가지는 단단 G-M냉동기를 개발하였고 설계 및 제작에 대한 원천기술을 확보할 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1925-1931
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• 2011

This paper suggests an approach to the subtle concept, "good", through the fuzzy logic and the design of the Canny edge detector of Gray scale images based on the rules of fuzzy anisotropic diffusion. The Canny edge detection algorithms design is to divide the gray levels into pixels and then calculate the diffusion coefficients at each pixel of non-edgy regions. Based on this processing, we present the Canny edge detector implementing fuzzy logic and comparing the results to other existing methods. The proposed approach is the narrow dynamic range of the gray-level image Sharpening the edge detection and has the advantage.

• Journal of Korea Multimedia Society
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• v.5 no.1
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• pp.38-46
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• 2002

In this paper, we present an adaptive contrast controller for improving the Quality of motion-picture in the video signals on the display. Using a median of image signals, we can improve the contrast according to the middle brightness, adaptively. In addition, the proposed method is useful for real-time image processing and can be composed of simpler hardware structure than other conventional methods because it does not require field and frame memory for computed data. The proposed method can be applied for video signals as well as the still image, while existing methods are confined to only the static image Also, we designed the algorithm through the VHDL, and implemented it through the FPGA. From the testing results, we see that the proposed method can effectively improve the image contrast.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.538-541
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• 2014

With the increased market demand for advanced specifications in smart phones, smart phones that have functions with wireless communications with high speed, cameras with high pixel and with high graphic processing ability have appeared. Furthermore, as traditional Augmented Reality technology has been practicable in mobile devices, many application's use AR technology, so AR's portability has been increased. But application with AR technology, which was implemented in smart phones has created capacity issues as applications are taking up a large portion of the memory capacity of phones. This research designed and implemented optimized AR technology by Mixare, AR open source, to solve such problems. As a result, I assured that there has been a decrease in application's memory used on the basis of mobiles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.4
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• pp.49-55
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• 2010

Cast shadow caused by an illumination condition can produce troublesome effects for face recognition system using reflectance image. Consequently, we need to separate cast shadow area from feature area for improvement of recognition accuracy. A Bilateral filter smooths image while preserving edges, by means of a nonlinear combination of nearby pixel values. Processing such characteristics, this method is suited to our purpose in illumination estimation process based on Retinex. Therefore, in this paper, we propose a new illumination normalization method based on the Bilateral filter in face images. The proposed method produces a reflectance image that is preserved relatively exact cast shadow area, because coefficient of filter is designed to multiply proximity and discontinuity of pixels in input image. Performance of our method is measured by a recognition accuracy of principle component analysis(PCA) and evaluated to compare with other conventional illumination normalization methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.6
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• pp.9-15
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• 2007

In this paper, we propose an efficient method for Processing DWT (Discrete Wavelet Transform) on GPU (Graphics Processing Unit). Since the DWT and EBCOT (embedded block coding with optimized truncation) are the most complicated submodules in JPEG2000, we design a high-performance processing framework for performing DWT using the fragment shader of GPU based on the render-to-texture (RTT) architecture. Experimental results show that the performance increases significantly, in which DWT running on modern GPU is more than 10 times faster than on modern CPU. Furthermore, by replacing the DWT part of Jasper which is the JPEG2000 reference software, the overall processing is 2$\sim$16 times faster than the original JasPer. The GPU-driven render-to-texture architecture proposed in this paper can be used in the general image and computer vision processing for high-speed processing.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.155.2-155.2
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• 2012

CTIO 4m 및 CTIO 1m 망원경으로 Westerlund 2의 UBVI 관측을 수행하여, CTIO 4m SDSS $u$ filter의 적색광누출 현상을 발견하였고 그 영향을 분석하였다. 적색광누출 현상은 filter의 투과함수가 설계와는 달리 장파장 영역에서 투과 존재하는 현상으로, CTIO 4m SDSS $u$ filter의 경우 B-V>1.4, V-I>2.0에서 그 영향이 나타나기 시작한다. SDSS $u$ filter의 적색광누출 현상은 별의 고유색지수와 상관없이 관측된 색지수가 클수록 영향이 크며, $B-V{\leq}1.8$, $V-I{\leq}2.8$의 범위에서는 보정이 가능하다. CTIO 1m B filter에서는 성간소광을 받지 않은 별과 성간소광을 많이 받은 별의 표준계변환 결과, $B_{CTIO1m}=B_{Standard}-0.055{\times}E(V-V)$에 해당하는 차이를 보였다. 이러한 차이는 CTIO 1m B filter의 투과함수의 단파장 쪽 날개부분이 표준 Johnson B filter에 비하여 단파장 쪽으로 많이 치우쳐있기 때문으로 보인다. 특히 Ballmer jump에 해당하는 파장인 370 nm에서 filter의 최대투과율에 비하여 32.2%에 달하는 투과율을 보이는데, 이는 Bessell B filter의 3.1%에 비하여 매우 큰 값이다. CTIO 1m 망원경의 Y4KCam CCD에서는 포화된 화소에 의한 crosstalk 뿐 아니라 포화되지 않은 화소에 의한 crosstalk 현상도 보였다. 짧은 노출을 준 영상에서는 5000 ADU 이상에서는 육안에 의한 crosstalk 확인이 가능하며, 포화되지 않은 밝은 별에 의한 crosstalk을 확인하지 않고 측광할 경우 백색왜성으로 오인할 가능성이 있으므로 측광 과정에서 좌표를 통하여 확인할 필요가 있다.