• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1169-1177
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• 2003

The blocking effect results from independent coding of each image block and becomes highly visible, especially coded at very low bit rates. In this paper, a blocking effect reduction circuit is designed which is composed of a memory, arithmetic and logic unit, and control block. The circuit is based on a rational open uniform B-spline curve that uses to produce a smooth curve through a set of control points. The weight values and the modified pixel values in a rational open uniform B-spline curve are calculated using arithmetic and logic circuits. The simulation results show that the circuit has excellent performance for ail pattern of the blocking effects.

• Journal of Biomedical Engineering Research
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• v.19 no.6
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• pp.551-562
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• 1998

Amultiresolution filtering algorithm based on the physical SPECT lesion detachability provides and optimal solution for SPECT reconstruction problem. Related to the previous study, we estimated the SPECT lesion detection capability by m minimum detectable lesion sizes (MDLSs), and generated m reconstruction filters which are designed to maximize the smoothing effect at a fixed MDLS-dependent resolution level $\frac{MDLS}{4\sqrt{2In2}}$. The proposed multiresolution filtering algorithm used a coarse-to-fine approach for the m-level resolution filter images obtained from these m filters for a given projection image. First, the local homogeneity is determined for every pixel of the filter images, by comparing the local variance value computed in a window centered at the pixel and the mode determined from the distribution of the local variances. Based on the local homogeneity, the pixels declared as homogeneous are chosen from the filter image of the lowest resolution, and for the other pixels the same process is repeated for the higher resolution filter images. For the non-homogeneous pixels after this pixels after this repetition process ends, the pixel values of the highest resolution filter image are substituted. From the results of the simulated experiments, the proposed multiresolution filtering algorithm showed a strong smoothing effect in the homogeneous regions and a significant resolution improvement near the edge regions of the projection images, and so produced good adaptability effects in the reconstructed images.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.27 no.1
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• pp.47-53
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• 2023

Devices such as X-Ray, CT, MRI, scanners, etc. can generate S&P noise from several sources during the image acquisition process. Since S&P noise appearing in the image degrades the image quality, it is essential to use noise reduction technology in the image processing process. Various methods have already been proposed in research on S&P noise removal, but all of them have a problem of generating residual noise in an environment with high noise density. Therefore, this paper proposes a filtering algorithm based on a three-dimensional plane equation by setting the grayscale value of the image as a new axis. The proposed algorithm subdivides the local mask to design the three closest non-noisy pixels as effective pixels, and applies cosine similarity to a region with a plurality of pixels. In addition, even when the input pixel cannot form a plane, it is classified as an exception pixel to achieve excellent restoration without residual noise.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.26-36
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• 2006

In this paper, we propose a cost-effective color filter may (CFA) demosaicing method for digital still cameras in which a single CCD or CMOS image sensor is used. Since a CFA is adopted, we must interpolate missing color values in the red, green and blue channels at each pixel location. While most state-of-the-art algorithms invest a great deal of computational effort in the enhancement of the reconstructed image to overcome the color artifacts, we focus on eliminating the color artifacts with low computational complexity. Using spatial correlation of the adjacent pixels, the edge-directional information of the neighbor pixels is used for determining the edge direction of the current pixel. We apply our method to the state-of-the-art algorithms which use edge-directed methods to interpolate the missing color channels. The experiment results show that the proposed method enhances the demosaiced image qualify from $0.09{\sim}0.47dB$ in PSNR depending on the basis algorithm by removing most of the color artifacts. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 12K, and five line memories are used.

• Journal of IKEEE
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• v.21 no.3
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• pp.268-271
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• 2017

In this paper, we propose the development of high resolution $360^{\circ}$ omnidirectional IP camera with 12 million pixels. The proposed 12-megapixel high-resolution $360^{\circ}$ omnidirectional IP camera consists of a lens unit with $360^{\circ}$ omnidirectional viewing angle and a 12-megapixel high-resolution IP camera unit. The lens section of $360^{\circ}$ omnidirectional viewing angle adopts the isochronous lens design method and the catadioptric facet production method to obtain the image without peripheral distortion which is inevitably generated in the fisheye lens. The 12 megapixel high-resolution IP camera unit consists of a CMOS sensor & ISP unit, a DSP unit, and an I / O unit, and converts the image input to the camera into a digital image to perform image distortion correction, image correction and image compression And then transmits it to the NVR (Network Video Recorder). In order to evaluate the performance of the proposed 12-megapixel high-resolution $360^{\circ}$ omnidirectional IP camera, 12.3 million pixel image efficiency, $360^{\circ}$ omnidirectional lens angle of view, and electromagnetic certification standard were measured.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.117-123
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• 2007

Catadioptric mirrors are widely used in automatic surveillance system. The major drawback of catadioptric mirror is its unequal image resolution. Equidistance catadioptric mirrir can be the solution to this problem. The exact axial alignment and the exact mount of mirror are the sources that can be avoided but the focal length variation is inevitable. In this paper, the effects of focal length variation on the computation of depth and height of object' point are explained and the effective and simple focal length finding algorithm is presented. First two object's points are selected, and the counterparts on the other stereo image are to be found using MSE criterion. Using four pixel distance from the image center, the assumed focal length is calculated. If the obtained focal length is different from the exact focal length, 24mm, the focal length value is modified by the proposed method. The method is very simple and gives the comparable results with the earlier sophisticated method.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.249-254
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• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.104-111
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• 2002

In this paper, we proposed the architecture of the decoder which implements the multi-view images decoding algorithm. The study of the hardware structure of the multi-view image processing has not been accomplished. The proposed multi-view images decoder operates in a three stage pipelined manner and extracts the depth of the pixels of the decoded image every clock. The multi-view images decoder consists of three modules, Node selector which transfers the value of the nodes repeatedly and Depth Extractor which extracts the depth of each pixel from the four values of the nodes and Affine transformer which generates the projecting position on the image plane from the values of the pixels and the specified viewpoint. The proposed architecture is designed and simulated by the Max+plus II design tool and the operating frequency is 30MHz. The image can be constructed in a real time by the decoder with the proposed architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.600-603
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• 2008

In this paper, a new circuit design named memory-in-pixel for low power consumption of the liquid crystal display (LCD) is presented. Since each pixel has a memory, it is able to express 8 color grades using the data saved in the memory without the operation of the gate and source driver ICs so that it can reduce the power consumption of the LCD panel. A memory circuit consists of modified S-R flip-flop (NAND-type) implemented in the pixel, which can supply AC bias for operating the liquid crystal (LC) with the interlocking clocks (CLK_A and CLK_B). This circuit is more complex than the inverter-type memory circuit, but it has lower power consumption of approximately 50% than the circuit. We have investigated the power consumption both NAND and inverter-type memory circuit using a Smart SPICE for the resolution of $96{\times}128$. The estimated power consumption of the inverter-type memory was about 0.037mW. On the other hand, the NAND-type memory showed power consumption of about 0.007mW.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.4
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• pp.23-28
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• 2002

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents the disconnection in the gray-scale image thinning. To extract the skeleton from the image in a real time, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture consists of three blocks, PS(Parallel to Serial) Converter and Stare Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examines the connectivity of the central pixel by searching the data from the PS Converter. The Ridge Checker determines whether the central pixel is on the skeleton or not. The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.