• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1844-1850
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• 2016

The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110nm standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416MHz of operating frequency with 132K gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.55-62
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• 2007

This paper proposes a defective pixel detection algorithm and its hardware structure for CCD/CMOS image sensor. In previous algorithms, the characteristics of image have not been considered. Also, some algorithms need quite a time to detect defective pixels. In order to make up for those disadvantages, the proposed defective pixel detection method detects defective pixels efficiently by considering the edges in the image and verifies them using several frames while checking scene-changes. Whenever scene-change is occurred, potentially defective pixels are checked and confirmed whether it is defective or not. Test results showed that the correct detection rate in a frame was increased 6% and the defective pixel verification time was decreased 60%. The proposed algorithm was implemented with verilog HDL. The edge indicator in color interpolation block was reused. Total logic gate count was 5.4k using 0.25um CMOS standard cell library.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.45-52
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• 2009

We proposed a new pixel circuit and driving method for the large-area, high-luminance AMOLED applications in this study. We designed with the low-temperature poly-silicon(LTPS) thin film transistors(TFTs) that has poor uniformity but stable characteristic. To improve the uniformity of an image, the threshold voltage($V_{TH}$) and the mobility of the TFTs can be compensated together. The proposed method overcomes the previous methods for mobility compensation, and that is profitable for large-area applications. Black data insertion was introduced to improve the characteristics for moving images. AMOLED panel can operate in two compensation mode, so the luminance degradation by mobility compensation can be released. The scan driver for controlling the pixel circuits were optimized, and the compensation mode can be controlled simply by that. Final driving signal has large timing margin, and the panel operates stably. The pixel circuit was designed for 14.1" WXGA top-emission ANGLED panel. The non-uniformity of the designed panel was estimated under 5% for the mobility compensation time of 1us.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of Internet Computing and Services
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• v.18 no.1
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• pp.21-26
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• 2017

In this paper, an USB-OTG (Uiversal Serial Bus On-the-go) interface module was designed with the iris information for personal identification. The image recognition algorithm which was searching face and iris areas, was proposed with pixel differences from eye blinking after several facial images were captured and then detected without any activities like as pressing the button of smart phone. The region of pupil and iris could be fast involved with the proper iris area segmentation from the pixel value calculation of frame difference among the images which were detected with two adjacent open-eye and close-eye pictures. This proposed iris recognition could be fast processed with the proper grid size of the eye region, and designed with the frame difference between the adjacent images from the USB-OTG interface with this camera module with the restrict of searching area in face and iris location. As a result, the detection time of iris location can be reduced, and this module can be expected with eliminating the standby time of eye-open.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1364-1366
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• 1998

An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay. pixel charging ratio, level-shift of the pixel voltage were simulated with varying the parameters. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.468-470
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• 2012

본 논문에서는 High Efficiency Video Coding (HEVC)을 하드웨어로 구현하기 위해서 파이프라인 방식을 인-루프 필터에 새롭게 도입된 기술인 Sample Adaptive Offset (SAO)에 적용하여 병렬화 처리하는 방법을 제안한다. 현재 HEVC 에서 SAO 의 입출력이 프레임단위로 구현되어 있는데, 이를 파이프라인 방식의 하드웨어 설계시에는 Largest Coding Unit(LCU)단위로 입출력이 가능하도록 수정해야 한다. SAO 에서 사용하는 두 가지 방식으로 Edge Offset(EO)과 Band Offset(BO)모드가 있으며, 이 중 EO 모드가 주변 화소값을 이용하므로 주변 화소값 정보가 없는 LCU 경계에 위치한 화소들을 버퍼에 저장한 뒤, 다음 LCU 블록의 입력과 함께 SAO 를 수행한다. 또한, SAO 앞 단의 인-루프 필터 기술인 디블록킹 필터(Deblocking Filter)에서도 LCU 단위로 입출력이 수행되므로 디블록킹 필터에서 저장하는 버퍼를 고려하면, SAO 입력에서 사용가능한 데이터는 LCU 가 천이된 형태가 된다. 따라서 SAO 입력의 천이된 형태와 버퍼 사용에 따라 총 9 가지 타입을 갖게 되며, 이 중 경계에 위치한 블록을 제외한 타입들의 경우 서로 다른 정보를 가진 SAO 를 4 번 수행해야 한다. 이러한 점을 반영한 파이프라인 방식을 SAO 에 적용하여 하드웨어에 적합한 구조를 구현할 수 있다.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.237-243
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• 2007

In this paper, we propose the Real-time Dead-Pixel Detection and Compensation System for mobile camera and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However a conventional Dead-Pixel Detection Algorithm is disable to detect neighboring dead pixels and it degrades image quality by wrong detection and compensation. To detect dead pixels the proposed system is classifying dead pixels into Hot pixel and Cold pixel. Also, the proposed algorithm is processing line-detector and $5{\times}5$ window-detector consecutively. The line-detector and window-detector can search dead pixels by using one-dimensional(only horizontal) method in low frequency area and two-dimensional(vertical and diagonal) method in high frequency area, respectively. The experimental result shows that it can detect 99% of dead pixels. It was designed in Verilog hardware description language and total gate count is 23K using TSMC 0.25um ASIC library.

• Journal of Digital Contents Society
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• v.9 no.1
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• pp.17-26
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• 2008

This paper has for its object to propose AFOD(Adaptive First-Order Decimator) which sets a value of decimated element as an average of a value of neighbor intelligible component and a output value of FOD(First-Order Decimator) for the target pixel, and to analyze its performance in terms of subjective image quality and hardware complexity. In the proposed AFOD, a target pixel located at the center of sliding window is selected first, then the gradient amplitudes of its right neighbor pixel and its lower neighbor pixel are calculated using first order derivative operator respectively. Secondly, each gradient amplitude is divided by the summation result of two gradient amplitudes to generate each local intelligible weight. Next, a value of neighbor intelligible component is defined by adding a value of the right neighbor pixel times its local intelligible weight to a value of the lower neighbor pixel times its intelligible weight. Since the proposed method adaptively reflects neighbor intelligible informations of neighbor pixels on the decimated element according to each local intelligible weight, it can effectively suppress the blurring effect being the demerit of FOD. It also possesses the advantages that it can keep the merits of FOD with the good results on average but also lower computational cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.