• Review of KIISC
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• v.18 no.3
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• pp.41-47
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• 2008

본 논문은 기존의 패스워드 인증 시스템의 취약점 문제 및 이에 대응하여 제안된 다수의 영상 기반 인증 시스템을 소개하고, 인증 과정에서 2차원 또는 3차원 영상 내의 이동하면서도 기억하기 쉬운 다수의 화소 정보에 기반을 둔 향상된 영상기반 전략을 소개한다. 최근 관심의 대상이 되고 있는 바와 같이, 인증 과정에서 입력되는 패스워드에 대한 감시 문제의 심각성에도 불구하고 그동안 취약한 사용자 신분증명에 대한 납득할 만한 대안이 부재하였다. 따라서 신중하게 설계된 보안 기반구조에도 불구하고 사용자 패스워드는 많은 응용에서 키보드 감시나 어깨너머로 훔쳐보기를 통하여 타인에게 쉽게 노출될 수 있다. 제안한 방안은 패스워드 인증에 문자열을 사용하지 않으므로 악의적 감시가 쉽지 않고, 소유자에게는 보다 기억하기 쉬우면서도 타인에게는 정보 노출을 최소화 할 수 있으므로 최근의 패스워드 유출 문제에 대한 훌륭한 대응책일 뿐만 아니라 키보드를 갖지 않는 휴대 장치를 위한 인증 방안으로도 활용 가능하다.

• Journal of the Korea Society for Simulation
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• v.10 no.3
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• pp.59-70
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• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

• Korean Journal of Optics and Photonics
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• v.12 no.5
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• pp.382-388
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• 2001

KITSAT-3, launched at May 26 1999, has an earth observation optical payload named MEIS (Multi-spectral Earth Imaging System). The MEIS is a Managin mirror telescope of aperture size of 95mm, and it images the ground with the ground sampling distance of 13.8m over 48km at the altitude of 720km using three different observations bands. This paper first presents the design and then the optics, relating results of manufacturing, integration and test. Finally it briefly discusses the current status of MEIS operation.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.183-184
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• 2009

영상 확대 기술을 담당하는 업스케일러를 설계 할 때 보간 기법의 선택은 매우 중요하다. 적용하는 보간 기법에 따라 출력되는 영상의 화질과 스케일러 내부의 연산량 및 하드웨어 복잡도가 결정되기 때문이다. 디지털 영상 처리 기술의 발달과 함께 성능이 좋은 여러 가지 보간 기법들이 개발되어 오고 있지만 알고리즘의 복잡도를 고려하지 않은 기법들은 실시간 처리와 하드웨어 적용에 부적합한 경우가 많다. 비교적 좋은 성능을 보여주는 Cubic interpolation 역시 인접 화소 보간 기법이나 선형 보간 기법과 비교하면 훨씬 더 많은 연산량을 요구한다. 이런 높은 연산량의 대부분은 픽셀의 밝기값에 곱해지는 계수를 구하기 위한 복잡한 계산에서 기인한다. 따라서 본 논문에서는 cubic interpolation 의 복잡도를 낮춰 하드웨어 적용에 적합하도록 하기 위하여 LUT(Look-up Table)을 이용하는 방법을 제안하고 실험을 통해 그 결과를 보인다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.34-41
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• 2010

We proposed the new pixel compensation circuit with high aperture ratio and the driving method for the large-area, low-power AMOLED applications in this study. We designed with the low-temperature poly-silicon(LTPS) thin film transistors(TFTs) that has poor uniformity but good mobility and stability. To lower the error rate of the pixel circuit and to improve the aperture ratio for bottom emission method, we simplified the pixel compensation circuit. Because the proposed pixel compensation circuit with high aperture ratio has very low contrast ratio for conventional driving methods, we proposed the new driving method and circuit for high contrast ratio. Black data insertion was introduced to improve the characteristics for moving images. The pixel circuit was designed for 19.6" WXGA bottom-emission AMOLED panel, and the average aperture ratio of the pixel circuit is improved from 33.0% to 41.9%. For the TFT's $V_{TH}$ variation of ${\pm}0.2\;V$, the non-uniformity and contrast ratio of the designed panel was estimated under 6% and over 100000:1 respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.5
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• pp.1180-1188
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• 2015

In this paper, we propose a new subband quantizer which is a type of quad-tree for applying to digital hologram compression based on Fresenelet transform. After executing Fresnelet transform to the captured digital holgoram, we analyze effect of the designed quantizer for the reconstructed objects from analyzing average energy of each coefficient and visual importance in all subbands. We analyze distribution of coefficient and set dynamic range for each subband, and then design subband quantizer. For enhancing effectiveness of the designed quantize, we adopt a method using the coefficients which are located out of dynamic range, which are named by exception indices. From this, we can obtain more effective quantizer which has higher performance in a range of σ′ = 5.0.

• Korean Journal of Optics and Photonics
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• v.15 no.5
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• pp.423-428
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• 2004

The development of a compact and high performance MWIR thermal imaging sensor based on the SOFRADIR 320${\times}$240 element IRCCD detector is described. The sensor has 20 magnification zoom optics with the maximum 40$^{\circ}$${\times}$30$^{\circ}$ of super wide field of view and 7.6 cycles/mrad of resolving power with the operation of attached micro-scanning system. In order to correct nonuniformities of detector arrays, we have proposed a multi-point correction method using defocusing of the optics and we have acquired the highest quality images. The MRTD of our system shows good results below 0.05K at spatial frequency 1 cycles/mrad at narrow field of view. Experimental data and obtained performances are presented and discussed.

• Korean Journal of Optics and Photonics
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• v.14 no.3
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• pp.236-243
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• 2003

We discussed the design of lens module schematic eyes equivalent to finite model eyes, which are used to model the human eye based on spherical aberration and Stiles-Crowford effect. The optical system for head mounted display (HMD) is designed and evaluated using lens module schematic eyes. In addition to a compact HMD system, an optical system with high Performance is required. To satisfy these requirements, we used diffractive optical elements and aspheric surfaces so that the color and mono-chromatic aberrations were corrected. The optical system for HMD is composed of 0.47 inch micro-display of SVGA grade with 480,000 pixels, a plastic hybrid lens for the virtual image, and the lens module schematic eyes. The designed optical system fulfills the current specifications of HMD: such as, EFL of 31.25 mm, FOV of 24H$\times$18V$\times$30D degrees, and overall length of 59.1 mm. As a result, we could design an optical system useful for HMD; the system is expected to be comfortable while the user wears it.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.