• Title/Summary/Keyword: 합성 제어

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Development of CPLD technology mapping control algorithm for Sequential Circuit under Time Constraint (시간제약 조건하에서 순차 회로를 위한 CPLD 기술 매핑 제어 알고리즘 개발)

  • Youn, Chung-Mo;Kim, Jae-Jin
    • Journal of the Korean Institute of Telematics and Electronics T
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    • v.36T no.4
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    • pp.71-81
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    • 1999
  • We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

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A VLSI Design of High Performance H.264 CAVLC Decoder Using Pipeline Stage Optimization (파이프라인 최적화를 통한 고성능 H.264 CAVLC 복호기의 VLSI 설계)

  • Lee, Byung-Yup;Ryoo, Kwang-Ki
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.50-57
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    • 2009
  • This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

Physical Properties of Sintered Body for Coal Fly Ash-clay Slip of Varying Dispersion State (석탄회-점토계 슬립의 분산상태에 따른 소결체의 물리적 특성)

  • 강승구;이기강;김유택;김정환
    • Journal of the Korean Ceramic Society
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    • v.40 no.7
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    • pp.677-682
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    • 2003
  • The physical properties of sintered body made from 3 kinds of slip, F (Flocculated), M (Moderate), and D (Dispersed) for coal fly ash 70-clay 30 (wt%) were studied in terms of slip states and pore size distribution of sintered bodies. The floc particle size distribution for slip F was wider than slip D and the slip F contained flocs larger than 11 $\mu\textrm{m}$. The pore size distribution of the green body of all slips ranged over 1∼4 $\mu\textrm{m}$. The pores smaller than 1 $\mu\textrm{m}$ almost disappeared during the sintering process, while the larger pore of 2.5∼3 $\mu\textrm{m}$ growed by 1 $\mu\textrm{m}$. The pore distribution for the green body of slip F became a narrow in width and high in height after sintering and the large pore limit in a slip F sintered body was 5.1 $\mu\textrm{m}$ which is smaller than that of other slip. The slip F rather flocculated was favorable over slip D well dispersed, in offering a higher compressive strength. From these results, the mechanical strength of sintered body is dependent on the pore distribution which could be controlled by dispersion state of the slips.

Fabrication of IMT-2000 Linear Power Amplifier using Current Control Adaptation Method in Signal Cancelling Loop (신호 제거 궤환부의 전류 제어 적응형 알고리즘을 이용한 IMT-2000용 선형화 증폭기 제작)

  • 오인열;이창희;정기혁;조진용;라극한
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.40 no.1
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    • pp.24-36
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    • 2003
  • The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

Seismic Behavior and Performance Evaluation of Uckling-restrained Braced Frames (BRBFs) using Superelastic Shape Memory Alloy (SMA) Bracing Systems (초탄성 형상기억합금을 활용한 좌굴방지 가새프레임 구조물의 지진거동 및 성능평가)

  • Hu, Jong Wan
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.33 no.3
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    • pp.875-888
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    • 2013
  • The researches have recently progressed toward the use of the superelastic shape memory alloys (SMAs) to develop new smart control systems that reduce permanent deformation occurring due to severe earthquake events and that automatically recover original configuration. The superelastic SMA materials are unique metallic alloys that can return to undeformed shape without additional heat treatments only after the removal of applied loads. Once the superelastic SMA materials are thus installed at the place where large deformations are likely to intensively occur, the structural system can make the best use of recentering capabilities. Therefore, this study is intended to propose new buckling-restrained braced frames (BRBFs) with superelastic SMA bracing systems. In order to verify the performance of such bracing systems, 6-story braced frame buildings were designed in accordance with the current design specifications and then nonlinear dynamic analyses were performed at 2D frame model by using seismic hazard ground motions. Based on the analysis results, BRBFs with innovative SMA bracing systems are compared to those with conventional steel bracing systems in terms of peak and residual inter-story drifts. Finally, the analysis results show that new SMA bracing systems are very effective to reduce the residual inter-story drifts.

Flexural performance evaluation of fiber reinforced segments with GFRP plate (GFRP plate를 적용한 섬유보강세그먼트의 휨성능 평가)

  • Oh, Ri-On;Park, Sung-Ki;Sung, Sang-Kyung;Lee, Jae-Young;Kim, Hwang-Hee
    • Journal of Korean Tunnelling and Underground Space Association
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    • v.20 no.5
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    • pp.839-854
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    • 2018
  • This study was performed to evaluate the performance of GFRP plate reinforced segments for TBM tunnel support. Recently, the SFRC segment has been applied to prevent local damage such as reduction of the amount of reinforcing bars of the segment, crack control and breakage. However, the steel fiber used in the SFRC segment has a problem of durability deterioration due to fiber corrosion. Compared with the RC segment, the maximum flexural load reduction of the SFRC segment hinders the broad application range of the TBM tunnel segment. Therefore, GFRP plate was considered as a stiffener for the maximum load increase of SFRC segment, and structural synthetic fiber without corrosive concern was used as a substitute for steel fiber. The flexural performance of the segment was evaluated by using the type of reinforcing fiber and GFRP plate thickness as the main parameters. As a result, the maximum load and the flexural toughness were increased by 21.78~23.03% and 0.5~7.96%, respectively, as compared with the segments reinforced with reinforcing fiber and GFRP plate of 3 mm thickness.

Synthesis of Silica Nanoparticles Having the Controlled Size and their Application for the Preparation of Polymeric Composites (크기가 제어된 실리카 나노입자 합성과 제조된 입자의 고분자계 복합재 응용)

  • Kim, Jong-Woung;Kim, Chang-Keun
    • Polymer(Korea)
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    • v.30 no.1
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    • pp.75-79
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    • 2006
  • Silica nanoparticles for polymeric dental restorative composites were prepared by Stober method, and then the effects of surface treatment of silica particles with Lmethacrylofpropyltrimethofsilane $(\gamma-MPS)$ on the dispersity of the silica particles in the organic matrix was investigated. Particles having various average size were prepared by using controlled amounts of tetraethylorthosilicate(TEOS), water, and catalyst and by changing solvent used for reaction. The site of particles prepared by using methanol as solvent was smaller than that prepared by using ethanol as solvent. In addition, the size of particles was increased by decreasing amounts of water and by increasing amounts of TEOS and catalyst. Hydrophobic silica nanoparticles was prepared by reacting hydrophilic nanoparticles with $\gamma-MPS$ to improve interfacial properties with organic matrix. Amounts of $\gamma-MPS$ per unit mass of the particles was increased by decreasing particle size. even though the amount of $\gamma-MPS$ per specific surface area were nearly the same regardless of the particle size. The dispersity of the silica particles in the organic matrix was improved when the surface treated silica particles were used for preparing the polymeric dental restorative composites.

Characteristics of $\textrm{Al}_2\textrm{O}_3$-SiC Composite Powder Prepared by SHS Process and its Sintering Behavior (SHS법에 의한 $\textrm{Al}_2\textrm{O}_3$-SiC 복합분말 제조 및 소결특성)

  • An, Chang-Yeong;Yun, Gi-Seok;Jeong, Jung-Chae;Won, Chang-Wan
    • Korean Journal of Materials Research
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    • v.9 no.8
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    • pp.817-824
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    • 1999
  • The $Al_2$$O_3$-SiC composite powder was prepared by Self-propagating High-Temperature Synthesis(SHS) process using $SiO_2$Al and C powders as raw material. The effects of the molar ratio in raw material, compaction pressure, initial temperature of reactants on the products and combustion process were studied. Self-propagating high temperature synthesis of $SiO_2$/Al/C system should be preheated above $400^{\circ}C$ owing to the low combustion temperature. As the result of the combustion reaction, the purity of final product became better than that of reactants. In this system, the optimum molar ratio of $SiO_2$:Al:C was 3.0:4.0:6.0. The free carbon was removed by roasting at $650^{\circ}C$ for 30min. In this study, pressureless sintering was very dffective both for controlling the disintegration of specimen with powder bed and for obtaining dense sintered-body at $1700^{\circ}C$. The sintered-body produced with hot-pressing was about 98% of the theoretical relative density.

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Implementation of the AMBA AXI4 Bus interface for effective data transaction and optimized hardware design (효율적인 데이터 전송과 하드웨어 최적화를 위한 AMBA AXI4 BUS Interface 구현)

  • Kim, Hyeon-Wook;Kim, Geun-Jun;Jo, Gi-Ppeum;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.15 no.2
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    • pp.70-75
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    • 2014
  • Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

ARC Discharge Sound Source in Underwater (수중 아-크 방전음원에 관한 연구)

  • Chang, Jea-Hwan;Chang, Jee-Won
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.21 no.1
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    • pp.12-18
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    • 1985
  • In general the impulse sound sources of underwater generated by electric arc discharge had used static energy of the charged capacitors. The author proposed an underwater arc discharge sound source using secondary voltage of high voltage transformer without capacitors. The arc discharge device was composed of a high voltage transformer and a switching system. The impulse current in the primary turn of the high voltage transformer is controlled by the switching system and inductive current of the secondary turn in the high voltage transformer is used in making impulsive arc discharge. A series of experiment have been carried out to observe the acoustic characteristics of the impulse sound source generated by the arc discharge. The results obtained were as follows: 1. Secondary current at the time of arc discharge keeps after ohm's law in the beginning and the maximum current flows out as soon as arc discharge breaks out. 2. A time difference between a start of applied current and a generation of arc discharge sound is the 3msec and it is generated arc sound when breaking down electric insulation at maximum voltage. 3. The sharper the end of electrodes and the higher the secondary voltage, the higher the sound pressure level. 4. Arc discharge sound was generated even at the distance of 100cm between electrodes and was stably reproductive at the gap of 1cm to 100cm. 5. Electric arc discharge sound wave is a shock wave of pulse-width of 0.15msec and spectral distribution of it is plenty of low frequency components less than 10 KHz.

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