• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Proceedings of the Korea Concrete Institute Conference
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• 2009.05a
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• pp.59-60
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• 2009

Steel fibers are recently well recognized for good composite/strengthening materials because of their ductile behavior and good performance on crack control and shear behavior compared to concrete materials. Especially, the great improvement in shear strength by steel fibers led researchers to be involved in many experimental studies. However, our understanding on the complex shear behavior of the steel fiber reinforced concrete(SFRC) members are still very limited, and the fundamental test data are also not enough. In this study, therefore, 4 SFRC specimens were fabricated and tested, from which the effectiveness of steel fibers as shear reinforcement were evaluated. The test results shows that the shear strength of SFRC members increases as the amount of steel fibers increases.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.974-978
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• 2003

The down-converter of the WCDMA Digital Optic Repeater is developed. Based on the system specifications, the structure of the down-converter is accomplished and its block diagram is drawn. The down-converter is implemented according to these block diagrams. Subsequently a low pass filter, an automatic level controlled attenuator, a frequency synthesizer and other components for the down-converter are designed and implemented, and a main board to integrate these modules is also manufactured. To reduce the noise floor of system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the down-converter and the entire system, the performance tests are accomplished to check the performance about the specifications.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.69-76
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• 2000

A dual-modulus prescaler divides the input signal by one of the moduli according to the control signal. In this paper, a new fast dual-modulus prescaler is proposed. The proposed prescaler has a ratioed-NOR structure different from a conventional ratioed-NAND structure. The proposed one can operate at a higher speed by using parallely connected NMOSs instead of using series-connected ones. HSPICE simulation results using HYUNDAI 0.65(m 2-poly 2-metal CMOS process parameters show that the maximum operating frequency of the proposed dual-modulus prescaler is 2.8㎓ with power consumption of 40.7㎽ at 5V supply voltage at $25^{\circ}C$. The proposed dual-modulus prescaler can be utilized for the frequency-synthesis in cellular radio front-ends.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.273-278
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• 2012

In this contribution, we design and implement an SPI hardware interface for the microprocessor to communicate with the MMC (Multi-Media Card) in an embedded system. Proposed architecture is compatible with the APB in AMBA bus architecture. Embedding OS in an embedded system means a big burden in terms of hardware and software ending up with performance decline. In this paper, we adopt the concept of SPI communication without using OS in the embedded system and implement in a form of FPGA chip. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency, which satisfied our target speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.435-444
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• 2002

In this paper, a novel packet scheduling algorithm, so-called the CSL algorithm is discussed, whereby the firewall property as well as the deterministic delay bound guarantee are supported in session level. Lots of simulation studies validate those properties of the CSL algorithm. The CSL algorithm is distingushable from the well- known EDD scheme in terms of the firewall property. Regarding the implementation complexity, the CSL algorithm turns out to be of 0(1) besides the sorting overhead. Owing to the maintained generic fair queueing structure in the CSL algorithm, a various fair queueing schemes can be applied with minor modification. For the TCP/IP network which is vulnerable to the misbehaving traffic sources, the firewall property of the CSL algorithm is quite useful for the advanced quality of services.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.10
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• pp.703-713
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• 2004

This paper presents the new obstacle avoidance method that is composed of vision and sonar sensors, also a navigation algorithm is proposed. Sonar sensors provide poor information because the angular resolution of each sonar sensor is not exact. So they are not suitable to detect relative direction of obstacles. In addition, it is not easy to detect the obstacle by vision sensors because of an image disturbance. In This paper, the new obstacle direction measurement method that is composed of sonar sensors for exact distance information and vision sensors for abundance information. The modified splitting/merging algorithm is proposed, and it is robuster for an image disturbance than the edge detecting algorithm, and it is efficient for grouping of the obstacle. In order to verify our proposed algorithm, we compare the proposed algorithm with the edge detecting algorithm via experiments. The direction of obstacle and the relative distance are used for the inputs of the fuzzy controller. We design the angular velocity controllers for obstacle avoidance and for navigation to center in corridor, respectively. In order to verify stability and effectiveness of our proposed method, it is apply to a vision and sonar based mobile robot navigation system.

• Current Industrial and Technological Trends in Aerospace
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• v.8 no.1
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• pp.45-54
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• 2010

The goal of the paper is to discuss the recent trend of the configuration of high resolution LEO(Low Earth Orbit) EO(Earth Observation) satellites. The satellite configuration is decided by considering several factors such as mission, payloads, launch vehicle, propulsion and attitude control module. The advent of commercial companies selling satellite's images in 2000's requires additional changes of the satellite system to be capable of obtaining many high resolution images quickly. In order to meet customer's needs, the overall configuration of satellites is designed to be compact and stable without the loss of structural integrity and reliability. Among design changes, the configuration change of satellites is treated intensively in the paper.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.104-112
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• 1989

A design automation method for sequential circuits implementation by mans of PLA is discussed, and an optimal state-code assignment algorithm to minimize the PLA area is proposed. In order to design sequential circuit automatically, DASL (Design Automation Support Language) [8] which is easy to describe and powerful to synthesize, is proposed and used to describe sequential circuit, An optimal statecode assignment algorithm which considers next states and outputs simultaneously is proposed, and by adopting this algorithm to various examples, the area of PLA is reduced by 10% comparing privious methods. This system is constructed to design microinstruction, FSM, VLSI control part synthesis.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.8
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• pp.676-683
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• 2016

In this paper, an adaptive nulling algorithm which can be used to form nulls in the direction of jammer or interference signals in array antennas of single port system is proposed. The proposed adaptive algorithm does not require a priori knowledge of the incoming signal direction and can be applied to the partially adaptive arrays. This algorithm is the combination of the PSO(Particle Swam Optimization) algorithm and the gradient-based perturbation adaptive algorithm, which shows stable nulling performance adaptively even on the moving jammer environment where the incident direction of the interference signal is changing with time.