• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.6
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• pp.25-31
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• 2014

When the public key e and the composite number n=pq are disclosed but not the private key d in an asymmetric-key RSA, message decryption is carried out by obtaining ${\phi}(n)=(p-1)(q-1)=n+1-(p+q)$ and subsequently computing $d=e^{-1}(mod{\phi}(n))$. The most commonly used decryption algorithm is integer factorization of n/p=q or $a^2{\equiv}b^2$(mod n), a=(p+q)/2, b=(q-p)/2. But many of the RSA numbers remain unfactorable. This paper therefore applies baby-step giant-step discrete logarithm and $2^k$-ary modular exponentiation to directly obtain ${\phi}(n)$. The proposed algorithm performs a reverse baby-step and $2^k$-ary adult-step. As a results, it reduces the execution time of basic adult-step to $1/2^k$ times and the memory $m={\lceil}\sqrt{n}{\rceil}$ to l, $a^l$ > n, hence obtaining ${\phi}(n)$ by executing within l times.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.84-94
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• 2006

In this paper, we propose the algorithm to reduce guard time of UWB MAC time slot for throughput gain. In the proposed draft by multiband ofdm alliance (MBOA), Guard time of each medium access slot (MAS) is composed of shortest inter-frame space (SIFS) and MaxDrift which is the time caused by maximum frequency offset among devices. In this paper, to reduceguard time means that we nearly eliminate MaxDrift term from guard time. Each device of a piconet computes relative frequency offset from the device initiating piconet using periodically consecutive transferred beacon frames. Each device add or subtract the calculated relative frequency offset to the estimated each MAS starting point in order to synchronize with calculated MAS starting point of the device initiating piconet. According to verification of simulations, if the frequency offset estimator is implemented with 8 decimal bit, the ratio of the wasted time to Superframe is always less than 0.0001.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.24-36
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• 2003

The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.43-54
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• 2007

This paper presents design and verification of a face detection hardware for real time application. Face detection algorithm detects rough face position based on already acquired feature parameter data. The hardware is composed of five main modules: Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, and Window Detection. It also includes on-chip Integral Image memory and Feature Parameter memory. The face detection hardware was verified by using S3C2440A CPU of Samsung Electronics, Virtex4LX100 FPGA of Xilinx, and a CCD Camera module. Our design uses 3,251 LUTs of Xilinx FPGA and takes about 1.96${\sim}$0.13 sec for face detection depending on sliding-window step size, when synthesized for Virtex4LX100 FPGA. When synthesized on Magnachip 0.25um ASIC library, it uses about 410,000 gates (Combinational area about 345,000 gates, Noncombinational area about 65,000 gates) and takes less than 0.5 sec for face realtime detection. This size and performance shows that it is adequate to use for embedded system applications. It has been fabricated as a real chip as a part of XF1201 chip and proven to work.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• The Magazine of the IEIE
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• v.11 no.5
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• pp.42-50
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• 1984

국내의 다음세대 컴퓨터 개발을 위한 VLSI 설계와 CAD 분야에 대한 연구 방향을 제시한다. 연구의 목표는 국제적으로 경쟁할 수 있는 VLSI 설계능력과 백만개 정도의 트랜지스터로 자성된 회로를 경제적으로 설계하기 위한 CAD 기술과 System의 확립이다. ·새로운 회로 구조와 알고리즘에 대한 연구 · CAD 도구와 언어의 개발에 관한 첨단 CAD 기술개발연구 · VLSI 설계에 필요한 CAD 도구 이용과 개발에 필요한 표준 인터페이스, 네트워킹, 컴퓨팅 하드웨어. 시스템 소프트웨어에 대한 연구등의 부분으로 크게 나눌 수 있다. 이용 가능한 CAD system을 평가하고 개선하며 첨단 CAD에 대한 소프트웨어와 하드웨어에 대해 · 컴퓨팅 하드웨어 · 프로그램 분위기 · 네트워킹 능력 ·자료 교환을 위한 표준인터페이스 등에 관해 조사분석도 병행한다. CAD에 관한 세부적인 연구 과제는 · 시스템 사양언어 · 설계 검증 ·시스템시뮬레이션· 설계 합성 · 설계 해석· 설계 방법론·디바이스와 공정 모델링 프로그램 등이다. 고속 계산용 VLSI에 관한 구조와 알고리즘은 행렬 계산을 위한 ·분산 배열 처리 회로 ·시스토릭 (Systolic) 배열 회로 ·셀률라(Cellular) 논리 회로 · 3차원 배열 회로 와 · 비규칙적 계산 알고리즘을 갖는 VLSI가 있다. VLSI설계훈련과 CAD 기술 축적을 위해 CAD enter를 설립하여 전국적인 CAD 네트워킹을 관계 연구소와 여러 대학에 가설하며, MPC 계획을 추진한다. VLSI설계 가능성이 입증되면 VLSI 설계능력을 더욱 향상 시키기 위해 0.5∼1.0mm기술의 silicon faundary를 설립한다. 연구 개발 조직은 대학, 산업체. 연구소가 삼위일체가 되어 수행될 수 있도록 연구 개발 위원회를 설치 운영하며 경쟁적이며 경제적으로 연구 업무를 집행하는 것이 바람직하다.았다.형질에 관여하는 귀전자에 미치는 기구에 대하여 검토할 여타가 있다고 보여진다. 분해능의 특징으로 미루어 앞으로는 레이저를 이용한 계측 방법이 그 주류를 이룰 것으로 사료된다. 우선 본 해설은 기체의 온도 및 농도의 광학적 측정방법중 Raman산란광 검출법에 대하여 실제로 측정하는 입장에서 간단히 소개한다.lity)이, 높은 $GA_3$함량에 기인된다'는 주장은 본실험(本實驗)으로 부인(否認)되었다. 따라서, 응용학적(應用學的) 측면에서 고려해 볼 때, 리베스식물(植物)의 육종기간 단축을 위한 모든 화아분화(花芽分化) 촉진 조치는 P.J.-식물(植物)이 20. node이상 생육하였을 때 취하는 것이 효율적인 것으로 결론 지어진다.앞당겨진 7月 셋째 週였다. 8. Culex (Culex) tritaeniorhynchus summoro년의 最大發生 peak는 1981年, 1982年 모두 8月 둘째 週였다. 9. Anopheles (Anopheles) sinensis의 最大發生 peak는 1981年에 7月 다섯째 週, 1982年은 2週 앞당겨진 7月 셋째 週였다. 10. 重要 3種의 最大 peak를 比城하면 Culex (Culex) pipiens pallens와 Anopheles (Anopheles) sinensis는 1981年과 1982年 모두 最大 peak時期가 同一하였으며, Culex (Culex) tritaeniorhynchus summoro년는 2年間 모두 8月둘째 週에 나타났다.osterior to manubrium and anterior to aortic arch) replacing the normal mediastinal fat. (2) In benign thymoma, the marging of the mass was smooth and the normal fat

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• Geophysics and Geophysical Exploration
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• v.25 no.4
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• pp.177-188
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• 2022

Recently, the application of distributed acoustic sensors (DAS), which can replace geophones and seismometers, has significantly increased along with interest in micro-seismic monitoring technique, which is one of the CO₂ storage monitoring techniques. A significant amount of temporally and spatially continuous data is recorded in a DAS monitoring system, thereby necessitating fast and accurate data processing techniques. Because event detection and seismic phase picking are the most basic data processing techniques, they should be performed on all data. In this study, a machine learning-based P, S wave phase picking algorithm was developed to compensate for the limitations of conventional phase picking algorithms, and it was modified using a transfer learning technique for the application of DAS data consisting of a single component with a low signal-to-noise ratio. Our model was constructed by modifying the convolution-based EQTransformer, which performs well in phase picking, to the ResUNet structure. Not only the global earthquake dataset, STEAD but also the augmented dataset was used as training datasets to enhance the prediction performance on the unseen characteristics of the target dataset. The performance of the developed algorithm was verified using K-net and KiK-net data with characteristics different from the training data. Additionally, after modifying the trained model to suit DAS data using the transfer learning technique, the performance was verified by applying it to the DAS field data measured in the Pohang Janggi basin.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.3
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• pp.199-206
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• 2023

This study utilizes deep learning algorithms to automatically classify construction waste into three categories: wood waste, plastic waste, and concrete waste. Two models, VGG-16 and ViT (Vision Transformer), which are convolutional neural network image classification algorithms and NLP-based models that sequence images, respectively, were compared for their performance in classifying construction waste. Image data for construction waste was collected by crawling images from search engines worldwide, and 3,000 images, with 1,000 images for each category, were obtained by excluding images that were difficult to distinguish with the naked eye or that were duplicated and would interfere with the experiment. In addition, to improve the accuracy of the models, data augmentation was performed during training with a total of 30,000 images. Despite the unstructured nature of the collected image data, the experimental results showed that VGG-16 achieved an accuracy of 91.5%, and ViT achieved an accuracy of 92.7%. This seems to suggest the possibility of practical application in actual construction waste data management work. If object detection techniques or semantic segmentation techniques are utilized based on this study, more precise classification will be possible even within a single image, resulting in more accurate waste classification

• Journal of Broadcast Engineering
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• v.27 no.1
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• pp.3-12
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• 2022

Image deblurring aims to remove image blur, which can be generated while shooting the pictures by the movement of objects, camera shake, blurring of focus, and so forth. With the rise in popularity of smartphones, it is common to carry portable digital cameras daily, so image deblurring techniques have become more significant recently. Originally, image deblurring techniques have been studied using traditional optimization techniques. Then with the recent attention on deep learning, deblurring methods based on convolutional neural networks have been actively proposed. However, most of them have been developed while focusing on better performance. Therefore, it is not easy to use in real situations due to the speed of their algorithms. To tackle this problem, we propose a novel deep learning-based deblurring algorithm that can be operated in real-time on HD resolution. In addition, we improved the training and inference process and could increase the performance of our model without any significant effect on the speed and the speed without any significant effect on the performance. As a result, our algorithm achieves real-time performance by processing 33.74 frames per second at 1280×720 resolution. Furthermore, it shows excellent performance compared to its speed with a PSNR of 29.78 and SSIM of 0.9287 with the GoPro dataset.