• Title/Summary/Keyword: 합성 알고리즘

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Design of Hardwired Variable Length Decoder for H.264/AVC (하드웨어 구조의 H.264/AVC 가변길이 복호기 설계)

  • Yu, Yong-Hoon;Lee, Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.11
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    • pp.71-76
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    • 2008
  • H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm (Radix-2 MBA 기반 병렬 MAC의 VLSI 구조)

  • Seo, Young-Ho;Kim, Dong-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.94-104
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    • 2008
  • In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

A Study on Parallel Performance Optimization Method for Acceleration of High Resolution SAR Image Processing (고해상도 SAR 영상처리 고속화를 위한 병렬 성능 최적화 기법 연구)

  • Lee, Kyu Beom;Kim, Gyu Bin;An, Sol Bo Reum;Cho, Jin Yeon;Lim, Byoung-Gyun;Kim, Dong-Hyun;Kim, Jeong Ho
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.46 no.6
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    • pp.503-512
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    • 2018
  • SAR(Synthetic Aperture Radar) is a technology to acquire images by processing signals obtained from radar, and there is an increasing demand for utilization of high-resolution SAR images. In this paper, for high-speed processing of high-resolution SAR image data, a study for SAR image processing algorithms to achieve optimal performance in multi-core based computer architecture is performed. The performance deterioration due to a large amount of input/output data for high resolution images is reduced by maximizing the memory utilization, and the parallelization ratio of the code is increased by using dynamic scheduling and nested parallelism of OpenMP. As a result, not only the total computation time is reduced, but also the upper bound of parallel performance is increased and the actual parallel performance on a multi-core system with 10 cores is improved by more than 8 times. The result of this study is expected to be used effectively in the development of high-resolution SAR image processing software for multi-core systems with large memory.

Prediction of Shore Tide level using Artificial Neural Network (인공신경망을 이용한 해안 조위예측)

  • Rhee Kyoung Hoon;Moon Byoung Seok;Kim Tae Kyoung;Oh jong yang
    • Proceedings of the Korea Water Resources Association Conference
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    • 2005.05b
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    • pp.1068-1072
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    • 2005
  • 조석이란, 해면의 완만한 주기적 승강을 말하며, 보통 그 승강은 1일 약 2회이나, 곳에 따라서는 1일 1회의 곳도 있다. 조석에 있어서는 이 밖에 수일의 주기를 갖는 약간 불규칙한 승강, 반년, 또는 1년을 주기로 하는 다소 규칙적인 승강까지 포함하여 취급한다. 그러나, 각 항만마다 갖는 특정적인 주기인 수분내지 수십분의 주기의 승강은 조석으로 취급하지 않는다. 조석은 해양의 제현상 중에서 예측가능성이 가장 큰 현장으로 이는 조석이 천체의 운행과 연관되기 때문이다. 조석이란 지구로부터 일정한 거리에서 각 고유의 속도를 가지는 적도상을 운행하는 무수의 가상천체에 기인하는 규칙적인 개개의 조석을 합성한 것이며 이 개개의 조석을 분조(Constituent)라 한다. 여기에서 사용되는 신경망 모형은 입력과 출력으로 구성되는 블랙박스 모형으로서 하나의 시스템을 병렬적으로 비선형적으로 구축할 수 있다는 장점 때문에 과거 하천유역의 강우-유출과정에서의 경우 유출현상을 해석하고 유출과정을 모형화 하기 위해 사용하였다. 본 연구에서는 기존의 조위 예측방법인 조화분석법이 아닌 인공신경망을 이용하여 조위예측을 실시하였다. 학습이라는 최적화 과정을 통해 구조와 기능이 복잡한 자연현상을 그대로 받아들여 축적시킴으로써 이를 지식으로 현상에 대한 재현능력이 뛰어나고, 또한 신경회로망의 연상기억능력에 적용하여 수학적으로 표현이 불가능한 불확실한 조위곡선에 적용하기에 유리한 장점을 가지고 있다. 본 연구의 목적은 과거 조위이론을 통해 이루었던 조위예측을 우리가 알기 쉬운 여러 기후인자(해면기압, 풍향, 풍속, 음력 등)에 따른 조위곡선을 예측하기 위해 신경망 모형을 이용하여 여수지역의 조위에 적용하여 비교 분석하고자 한다. May가 제안한 공식을 더 확장하여 적용할 수 있는 실험 공식으로 개선하였으며 다양한 조건에 대한 실험을 수행하여 보다 정밀한 공식으로 개선할 수 있었다.$10,924m^3/s$ 및 $10,075m^3/s$로서 실험 I의 $2,757m^3/s$에 비해 통수능이 많이 개선되었음을 알 수 있다.함을 알 수 있다. 상수관로 설계 기준에서는 관로내 수압을 $1.5\~4.0kg/cm^2$으로 나타내고 있는데 $6kg/cm^2$보다 과수압을 나타내는 경우가 $100\%$로 밸브를 개방하였을 때보다 $60\%,\;80\%$ 개방하였을 때가 더 빈번히 발생하고 있으므로 대상지역의 밸브 개폐는 $100\%$ 개방하는 것이 선계기준에 적합한 것으로 나타났다. 밸브 개폐에 따른 수압 변화를 모의한 결과 밸브 개폐도를 적절히 유지하여 필요수량의 확보 및 누수방지대책에 활용할 수 있을 것으로 판단된다.8R(mm)(r^2=0.84)$로 지수적으로 증가하는 경향을 나타내었다. 유거수량은 토성별로 양토를 1.0으로 기준할 때 사양토가 0.86으로 가장 작았고, 식양토 1.09, 식토 1.15로 평가되어 침투수에 비해 토성별 차이가 크게 나타났다. 이는 토성이 세립질일 수록 유거수의 저항이 작기 때문으로 생각된다. 경사에 따라서는 경사도가 증가할수록 증가하였으며 $10\% 경사일 때를 기준으로 $Ro(mm)=Ro_{10}{\times}0.797{\times}e^{-0.021s(\%)}$로 나타났다.천성 승모판 폐쇄 부전등을 초래하는 심각한 선

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A Multi-sensor basedVery Short-term Rainfall Forecasting using Radar and Satellite Data - A Case Study of the Busan and Gyeongnam Extreme Rainfall in August, 2014- (레이더-위성자료 이용 다중센서 기반 초단기 강우예측 - 2014년 8월 부산·경남 폭우사례를 중심으로 -)

  • Jang, Sangmin;Park, Kyungwon;Yoon, Sunkwon
    • Korean Journal of Remote Sensing
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    • v.32 no.2
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    • pp.155-169
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    • 2016
  • In this study, we developed a multi-sensor blending short-term rainfall forecasting technique using radar and satellite data during extreme rainfall occurrences in Busan and Gyeongnam region in August 2014. The Tropical Z-R relationship ($Z=32R^{1.65}$) has applied as a optimal radar Z-R relation, which is confirmed that the accuracy is improved during 20mm/h heavy rainfall. In addition, the multi-sensor blending technique has applied using radar and COMS (Communication, Ocean and Meteorological Satellite) data for quantitative precipitation estimation. The very-short-term rainfall forecasting performance was improved in 60 mm/h or more of the strong heavy rainfall events by multi-sensor blending. AWS (Automatic Weather System) and MAPLE data were used for verification of rainfall prediction accuracy. The results have ensured about 50% or more in accuracy of heavy rainfall prediction for 1-hour before rainfall prediction, which are correlations of 10-minute lead time have 0.80 to 0.53, and root mean square errors have 3.99 mm/h to 6.43 mm/h. Through this study, utilizing of multi-sensor blending techniques using radar and satellite data are possible to provide that would be more reliable very-short-term rainfall forecasting data. Further we need ongoing case studies and prediction and estimation of quantitative precipitation by multi-sensor blending is required as well as improving the satellite rainfall estimation algorithm.

An Object-Based Verification Method for Microscale Weather Analysis Module: Application to a Wind Speed Forecasting Model for the Korean Peninsula (미기상해석모듈 출력물의 정확성에 대한 객체기반 검증법: 한반도 풍속예측모형의 정확성 검증에의 응용)

  • Kim, Hea-Jung;Kwak, Hwa-Ryun;Kim, Sang-il;Choi, Young-Jean
    • The Korean Journal of Applied Statistics
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    • v.28 no.6
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    • pp.1275-1288
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    • 2015
  • A microscale weather analysis module (about 1km or less) is a microscale numerical weather prediction model designed for operational forecasting and atmospheric research needs such as radiant energy, thermal energy, and humidity. The accuracy of the module is directly related to the usefulness and quality of real-time microscale weather information service in the metropolitan area. This paper suggests an object based verification method useful for spatio-temporal evaluation of the accuracy of the microscale weather analysis module. The method is a graphical method comprised of three steps that constructs a lattice field of evaluation statistics, merges and identifies objects, and evaluates the accuracy of the module. We develop lattice fields using various evaluation spatio-temporal statistics as well as an efficient object identification algorithm that conducts convolution, masking, and merging operations to the lattice fields. A real data application demonstrates the utility of the verification method.

Design of Low-complexity FFT Processor for Multi-mode Radar Signal Processing (멀티모드 레이다 신호처리를 위한 저복잡도 FFT 프로세서 설계)

  • Park, Yerim;Jung, Yongchul;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.24 no.2
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    • pp.85-91
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    • 2020
  • Recently, a multi-mode radar system was designed for efficient operation of unmanned aerial vehicles (UAVs) in various environments, which has the advantage of being able to integrate and utilize methods of the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar. For the range detection part of the multi-mode radar signal processor (RSP), the hardware structure using the FFT processor and the IFFT processor is required to be designed in a way that improves efficiency on the area side. In addition, given the radar application environment that requires a variety of distance resolutions, FFT processors need to support variable-length operations. In this paper, the FFT processor and IFFT processor in multi-mode RSP range estimation are designed and proposed as hardware for a single FFT processor that supports variable length operation of 16-1024 points. The proposed FFT processor designed in hardware description language (HDL) and can be implemented with 7,452 logic elements and 5,116 registers.

The Analysis and Design of Advanced Neurofuzzy Polynomial Networks (고급 뉴로퍼지 다항식 네트워크의 해석과 설계)

  • Park, Byeong-Jun;O, Seong-Gwon
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.39 no.3
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    • pp.18-31
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    • 2002
  • In this study, we introduce a concept of advanced neurofuzzy polynomial networks(ANFPN), a hybrid modeling architecture combining neurofuzzy networks(NFN) and polynomial neural networks(PNN). These networks are highly nonlinear rule-based models. The development of the ANFPN dwells on the technologies of Computational Intelligence(Cl), namely fuzzy sets, neural networks and genetic algorithms. NFN contributes to the formation of the premise part of the rule-based structure of the ANFPN. The consequence part of the ANFPN is designed using PNN. At the premise part of the ANFPN, NFN uses both the simplified fuzzy inference and error back-propagation learning rule. The parameters of the membership functions, learning rates and momentum coefficients are adjusted with the use of genetic optimization. As the consequence structure of ANFPN, PNN is a flexible network architecture whose structure(topology) is developed through learning. In particular, the number of layers and nodes of the PNN are not fixed in advance but is generated in a dynamic way. In this study, we introduce two kinds of ANFPN architectures, namely the basic and the modified one. Here the basic and the modified architecture depend on the number of input variables and the order of polynomial in each layer of PNN structure. Owing to the specific features of two combined architectures, it is possible to consider the nonlinear characteristics of process system and to obtain the better output performance with superb predictive ability. The availability and feasibility of the ANFPN are discussed and illustrated with the aid of two representative numerical examples. The results show that the proposed ANFPN can produce the model with higher accuracy and predictive ability than any other method presented previously.

A Study on the VLSI Design of Efficient Color Interpolation Technique Using Spatial Correlation for CCD/CMOS Image Sensor (화소 간 상관관계를 이용한 CCD/CMOS 이미지 센서용 색 보간 기법 및 VLSI 설계에 관한 연구)

  • Lee, Won-Jae;Lee, Seong-Joo;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.26-36
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    • 2006
  • In this paper, we propose a cost-effective color filter may (CFA) demosaicing method for digital still cameras in which a single CCD or CMOS image sensor is used. Since a CFA is adopted, we must interpolate missing color values in the red, green and blue channels at each pixel location. While most state-of-the-art algorithms invest a great deal of computational effort in the enhancement of the reconstructed image to overcome the color artifacts, we focus on eliminating the color artifacts with low computational complexity. Using spatial correlation of the adjacent pixels, the edge-directional information of the neighbor pixels is used for determining the edge direction of the current pixel. We apply our method to the state-of-the-art algorithms which use edge-directed methods to interpolate the missing color channels. The experiment results show that the proposed method enhances the demosaiced image qualify from $0.09{\sim}0.47dB$ in PSNR depending on the basis algorithm by removing most of the color artifacts. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 12K, and five line memories are used.

A Study on Reliability Based Design Criteria for the Steel Highway Bridge (강도로교(鋼道路橋)의 신뢰성(信賴性) 설계규준(設計規準)에 관한 연구(硏究))

  • Cho, Hyo Nam;Kim, Woo Seok;Lee, Cheung Bin
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.5 no.1
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    • pp.43-53
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    • 1985
  • This study proposes a reliability based design criteria for the steel bridge (H-beam, plate-girder and composite-beam), which is most common type of steel bridge, and also proposes the theoretical bases of nominal safety factors as well as load and rasistance factors based on the reliability theory. Major 2nd moment reliability analysis and design theories including both Cornell's MFOSM (Mean First Order 2nd Moment) Methods and Lind-Hasofer's AFOSM(Advanced First Order 2nd Moment) Methods are summarized and compared, and it has been found that Lind-Hasofer's approximate and an approximate Log-normal type reliability formula are well suited for the proposed reliability study. A target reliability index (${\beta}_0=3.5$) is selected as an optimal value considering our practice based on the calibration with the safety pravisions of the current steel bridge design code. Galambo's theory is used for the derivation of the algorithm for the evaluation of uncertainties associated with resistences by LRFD Format and SGST Format, whereas the magnitude of the uncertainties associated with load effects are chosen primarily by considering our level of practice. It may be concluded that the proposed LRFD reliability based design provisions for the steel highway bridge give more rational design than the current standard code for steel highway bridge.

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