• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.973-974
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• 2008

As radar signal environments become denser and more complex, the capability of high-speed and accurate signal analysis is required for ES(Electronic warfare Support) system to identify individual radar signals at real-time. In this paper, we propose the new novel clustering algorithm of radar pulses to alleviate the load of signal analysis process and support reliable analysis. The proposed algorithm uses KDE(Kernel Density Estimation) and its CDF(Cumulative Distribution Function) to compose clusters considering the distribution characteristics of pulses. Simulation results show the good performance of the proposed clustering algorithm in clustering and classifying the emitters.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.97-100
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• 2002

A procedural interface libary for IEEE Verilog 1364-2001 is developed. The lexer and scanner are developed to handle “Verilog-2001” which is the first major update to the Verilog language since its inception in 1984. Also the newly developed XML intermediate format for Verilog-2001 is Presented in the paper. By using the XML intermediate, it allows the portable and scalable development of various kinds of applications. The XML DTD(Document Type Definition) of Verilog is defined and the corresponding XML intermediate format is developed. The paper describes example application of code rule checker which is built using the language interface library.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.289-292
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• 2002

In this paper, an efficient architecture for the finite field multiplier is proposed. This architecture is faster and smaller than any other LFSR architectures. The traditional LFSR architecture needs t x m registers for achieving the t times speed. But, we designed He multiplier using a novel fast architecture without increasing the number of registers. The proposed multiplier is verified with a VHDL description using SYNOPSYS simulator. The measured results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier. The proposed multiplier is expected to become even more advantageous in the smart card cryptography processors.

• 전자공학회논문지A
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• 제33A권5호
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• 전자공학회지
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• 제23권11호
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• pp.23-33
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• 1996

본 논문은 원판과 전용 CAD 틀로 구성되는 FPGA시스템을 개발하는데 있어서 서로 다른 요소 기술들의 관계와 이들 요소 기술들과 시스템성능의 관계를 모델하여 시스템 사양을 만족하기 위하여 가장 효율적인 방법을 찾게하는 방법에 관한 것이다. 본 논문에서는 실제로 개발된 시스템을 예로 하여 FPGA시스템 개발에서 고려해야 할 점들을 고찰하였다. 새로운 FPGA 시스템의 개발 순서는 먼저 개발할 FPGA의 응용 분야를 결정하고, 그 응용 분야에 필요한 시스템 사양에 맞게 개발한 요소 기술들과 그 기술들의 범위를 정한다. 개발 흐름도를 이용하여 이 요소 기술들의 연관 관계를 수직적으로는 시스템 성능에 미치는 영향을 모델링하고 수평적으로는 요소 기술간의 서로 미치는 영향을 모델링 하여 시스템 사양을 만족하기 위한 최적의 해를 구한다. 이때 최종적인 FPGA 시스템을 평가하고 검증할 수 있는 방법을 결정한다. 요소 기술들이 개발 됨에 따라 좀 더 구체적이고 정확한 모델에 의해 전체 시스템의 성능은 평가되고 검증될 수 있다. 이러한 방법과 환경은 FPGA 시스템을 빠르고 효율적으로 개발할 수 있게 한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.267-269
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• 2002

This paper presents the static characteristics of PMLSM considering the slotting effects of the primary core. To estimate the force ripple, PMLSM is analysed by the theoretical analysis and the F.E.M. The simulation values are compared with experimental ones.

• 한국전기전자재료학회논문지
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• 제14권3호
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• pp.257-262
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• 2001

Single crystalline films of La doped YIG(yttrium iron garnet) were grown by the liquid phase epitaxy. The lattice constants of films obtained by DCD(double crystalline diffractometer) measurement increased with increasing La contents in films. In particular, lattice constants of films grown wiht Y/La=20 solution were nearly same as those of GGG (gadolinium gallium garnet) substrate. The saturation magnetization measured with VSM (vibrating sample magnetometer) was about 1750Gauss which is the same as that of pure YIG irrespective of La contents in films. FMR(ferromagnetic resonance) linewidth of La doped YIG was smaller than that of pure YIG. Since appropriate La doping decreases the lattice mismatch between film and substrate, the FMR linewidth was Y/La=20 in this experiment.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.776-780
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• 2000

ZnGa$_2$O$_4$thin films were prepared on Si(100) wafer in terms of RF power, substrate temperatures and Ar/O$_2$flow rate by RF Magnetron Sputtering. Photoluminescence(PL) measurement was employed to observe the emission spectra of ZnGa$_2$O$_4$films. The influences of various deposition parameters on the properties of grown films were studied. The optimum substrate deposition temperature for luminous characteristics was about 50$0^{\circ}C$ in this investigation. PL spectrum of ZnGa$_2$O$_4$ thin films showed broad band luminescence spectrum.

• 한국전기전자재료학회논문지
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• 제17권5호
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• pp.526-529
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• 2004

The nematic liquid crysta](NLC) aligning capabilities using a-C:H thin film deposited at the three kinds of rf bias condition were investigated. A high pretilt angle of NLC on low substrate rf bias applied a-C:H thin films was observed and the low pretilt angle of the NLC on high substrate rf bias applied a-C:H thin films was observed. Consequently, the high NLC pretilt angle and the good aligning capabilities of LC alignment by the IB alignment method on the a-C:H thin film deposited at 1 W rf bias condition can be achieved. It is considered that pretilt angle of the NLC may be attributed to substrate rf bias condition and IB energy time. Therefore, LC alignment is affected by topographical structure forming strong IB energy.

• 한국전기전자재료학회논문지
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• 제15권12호
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• pp.1075-1078
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• 2002

This paper describes on the design structure and development of temperature stable strip-line function isolator operating In above resonance mode. Temperature characteristics of isolator depend on magnet, YIG(Yttium Iron Garnet) ferrite, and conductor etc. These require temperature stability and possible methods of compensation for the temperature dependent effects. In this paper, the analysis and measurement of the temperature characteristics were carried out for the material isolator prototype. The bandwidth of isolator was expended and the frequency shift at center was reduced in the temperature range of -20∼80$\^{C}$.