• Title/Summary/Keyword: 하이라인

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Effects of Dietary Green Tea on Egg Storage in Laying Hens Under Stress (녹차의 급여가 스트레스하의 산란계가 생산한 계란의 저장성에 미치는 영향)

  • Kim, Jimin;Yoon, Hyung-Sook;Choi, Yang-Ho
    • Korean Journal of Organic Agriculture
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    • v.22 no.4
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    • pp.815-823
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    • 2014
  • Green tea has been known to show beneficial effects on alleviating stress. The present study was conducted to determine the effects of dietary green tea on quality of eggs, during storage, laid by laying hens treated with corticosterone in order to mimic the current practice of the egg market. Hens were fed for 2 weeks one of three diets containing green tea at 0.0, 0.4 or 1.0%. Each dietary group was divided into two subgroups receiving corticosterone at 0 or 30 mg/kg for 1 week. Eggs, laid at 5-7 days following the initiation of corticosterone treatment, were stored at $10^{\circ}C$ for 1 or 5 weeks and then analyzed for egg quality. After 1 week of storage, egg weight was significantly increased by green tea (p<0.025) but decreased by corticosterone (p<0.0001), but no interaction was observed between both. Corticosterone decreased shell color (p<0.0001) but green tea significantly decreased shell strength (p<0.006). Yolk color, albumen height and Haugh unit were not affected by both treatments. After 5 weeks of storage, corticosterone resulted in reduced egg weight (p<0.01) and eggshell color (p<0.001) and increased shell strength, which were not attenuated by green tea. Taken together, the results of the current study show that dietary corticosterone reduces egg quality during storage, which are attenuated in part by dietary green tea.

Effects of Dietary Hydrolyzed Yeast on Egg Production and Egg Quality during Late Phase of Laying Hens (산란후기 사료 내 가수분해 효모의 첨가 급여가 생산성과 계란 품질에 미치는 영향)

  • Chung, Jae Young;Kim, Kwan Eung;Lee, Hyung Ho;Yang, Hoi Chang;Kim, Eun Jib;An, Byoung Ki
    • Korean Journal of Poultry Science
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    • v.48 no.4
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    • pp.169-176
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    • 2021
  • An experiment was conducted to investigate the effects of varying levels of hydrolyzed yeast on egg production and egg quality in aged laying randomly allotted to three dietary treatments such that egg production was similar in each treatment (6 replicates of 10 birds each). The layers were fed diets containing 0, 0.1, or 0.2% hydrolyzed yeast for eight weeks. No significant difference was observed in egg production during the first half of the experiment. Egg production and daily egg mass in groups fed diets containing hydrolyzed yeast were significantly higher (P<0.05) than those of the control groups during the second half of the experiment. Egg weight was not affected by the dietary treatment. Eggshell strength and thickness in groups fed diets containing hydrolyzed yeast were significantly higher than those of the control groups during the overall experimental period (P<0.05). Although no significant differences were observed in the Haugh units, yolk color in the group fed diets containing 0.1% hydrolyzed yeast was significantly higher than that in the control group (P<0.05). The mammillary layer thickness increased in a linear manner and significantly following treatment with dietary hydrolyzed yeast (P<0.05). Antibody titer against avian influenza virus in the group fed diets containing 0.2% hydrolyzed yeast was significantly higher (P<0.05) than that in the control group. In conclusion, dietary hydrolyzed yeast improved egg production and eggshell quality of laying hens in the late stages of production.

Design and Implementation of Low power ALU based on NCL (Null Convention Logic) (NCL 기반의 저전력 ALU 회로 설계 및 구현)

  • Kim, Kyung Ki
    • Journal of Korea Society of Industrial Information Systems
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    • v.18 no.5
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    • pp.59-65
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    • 2013
  • Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

The Method of Addition Subexpression for High-Speed Multiplierless FIR Filters (곱셈기를 사용하지 않은 고속 FIR 필터를 위한 부분 항 덧셈 방법)

  • Kim, Yong-Eun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.8
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    • pp.32-36
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    • 2008
  • Multiplierless FIR filters can be designed by only adders using Common Subexpression algorithm. It has small area compared with filter which using multipliers. But it has long operation time because of carry ripple from the adder. In this paper, when the subexpressions are added in multiplier less filters, the number of subexpressions maintains 2 until final addition to avoid carry ripple of the addition, so the subexpression addition time of the filter can be reduced. To verify proposed method, subexpression adder circuit of the FIR filter is designed using given example of paper. The designed filter was synthesized using Hynix 0.18um process. By Synopsys simulation results, it is shown that by the proposed method, area, propagation delay time can be reduced up to 53.2%, 57.9% compared with conventional design method which using pipeline.

An Animated Documentary Study of Korean Youth Culture and Identity (한국 청소년들의 온라인 게임문화와 정체성에 관한 애니메이션 다큐멘터리 연구)

  • Park, Man
    • Cartoon and Animation Studies
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    • s.45
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    • pp.397-415
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    • 2016
  • This paper will investigate how animated practice can be a research form as practice-led research in an ethnography approach. This practice-led research will explore the issue of the construction of contemporary identities (based on the strange case of Dr. Jekyll and Mr. Hyde) and in particular, the Korean youth culture and identity, exemplified, for example, creation of 'avatars' in the virtual characters of animated online games such as Massively Multiplayer Online Role-playing Games (MMORPGs). In this proposed discussion, I will argue that the sudden period of change in contemporary Korea bears some resemblance to the Victorian era as explored in gothic fiction (e.g. Jekyll and Hyde). In this sense, my animation investigates the connection between the fictional Jekyll and Hyde and a real murder incident by a young Korean boy, which actually happened on the 16th November 2010, in SouthKorea.I will, therefore, construct this practice-led research to obtain the primary data consisted of online and offline practices in 'social ethnography'. These practices engage with specific Korean youth identity, comparing the 'avatar' with the real lives of participants. However, this paper will only focus on the (ethnographic) research process and strategy, using animated (visual) practices, rather than giving the meaning of the specific case of 'Korean-ness'. Eventually, I will explore the four different animated representations as it presents the distinctive animated realties or documentaries by online and offline practices. My intention is to visually interpret the issue of 'Korean-ness' within its socio-cultural context, adapting the convention and code of Jekyll and Hyde concept into an animated documentary in the 'virtual' world (auto-animated documentary by recording avatar interviews and online game footages) and the 'real' world (self-created animated documentary, based on real people and events).

Analysis of Marketing Strategy in Domestic Online Luxury Fashion Platform (국내 온라인 명품 패션 플랫폼 마케팅전략 분석)

  • Min Gyung Lee;Hyeon Ju Kim
    • The Journal of the Convergence on Culture Technology
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    • v.9 no.1
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    • pp.361-372
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    • 2023
  • In this study, three luxury fashion start-up platforms, Balaan, Trenbe, and Must-it, were selected as research subjects. The purpose of this study is to compare and analyze the marketing mix strategies of each of the three online sites. The results of our study are as follows. First of all, the product strategies of the three luxury platform companies are characterized by the composition of products from high-end brands to SPA brands, and product composition such as kids, home living, Used goods and art in addition to women's and men's wear. In addition, the pricing strategies of luxury platforms show price differences depending on the luxury platform even for the same product. It is shown as a structure that directly determines margin. Therefore, in order to secure an edge in price competitiveness, each platform provided discount coupons and savings that are not available in offline stores such as department stores, providing opportunities to purchase luxury goods at a lower price than offline stores.Lastly, the sales promotion strategies of the three luxury platform companies was used include price discount promotions such as price discounts, discount coupons, and regular sales, and value-added sales such as membership registration/review points, events, product information, delivery services, social contribution activities, and SNS utilization.

Development of Ground Plan a Measuring Instrument for Quality Assurance (품질확보를 위한 평면도 측정기 개발)

  • Mim, Byeong-Ro;Kim, Duck-Ki;Jun, Yoo-Hea;Jung, Jun-Hee;Lee, Hwen;Yoo, Su-Ho;Cha, San-Lee;Lee, Dae-Weon;OH, Se-Bu
    • Proceedings of the Korean Society for Agricultural Machinery Conference
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    • 2017.04a
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    • pp.151-151
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    • 2017
  • 본 연구는 인력을 이용한 품질검사를 수행하고 있는 현장에서 불량 및 품질에 대한 신뢰성이 떨어지고 있는 현상을 해소하기 위해 자동으로 평면도를 측정하고자 하였다. 설계는 Auto CAD를 이용하였다. 평면도 측정기의 크기는 가로${\times}$세로${\times}$높이를 $1000{\times}600{\times}1800mm$로 하였다. 프레임은 $60{\times}60$ 프로파일을 이용하였고 다른 구성 부품은 SUS304 재질을 이용하였다. 측정대상을 올려놓은 상태에서 녹색 버튼을 누루면 작동되도록 되어 있다. 그림 8은 측정결과를 나타낸 것이다. 측정기는 국내업체인 데바의 모델명 EA-20N의 Air Micrometer을 사용하였으며 측정핀의 위치는 조정이 가능하도록 하였다. 평면도 측정 중 설정치수와 같이 않으면 NG 명령과 함께 부저가 울리도록 프로그램하였다. 불량이 발생하면 그림 8과 같이 나타났다. 불량 측정을 위해 측정부의 결과 값이 나타나며 불량이 발생하면 어느 위치에서 불량이 발생했는지를 알 수 있도록 하였다. 또한 결과 값은 자동으로 저장되도록 하였다. 품질확보를 위해 100EA를 측정한 결과 0.00258, 0.00259, 0.00259, 0.00263, 0.00251, 0.00286, 0.00275의 평균값을 나타냈다. 측정값의 검증은 하이트게이지로 측정한 결과 0.002 이내의 결과를 나타냈다. 따라서 본 평면도 측정기를 이용한다면 생산성 향상이 가능하여 가격경쟁력이 있다고 판단된다.

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A 60 GHz Bidirectional Active Phase Shifter with 130 nm CMOS Common Gate Amplifier (130 nm CMOS 공통 게이트 증폭기를 이용한 60 GHz 양방향 능동 위상변화기)

  • Hyun, Ju-Young;Lee, Kook-Joo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.11
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    • pp.1111-1116
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    • 2011
  • In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.

An Efficient Test Method for a Full-Custom Design of a High-Speed Binary Multiplier (풀커스텀 (full-custom) 고속 곱셈기 회로의 효율적인 테스트 방안)

  • Moon, San-Gook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.830-833
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    • 2007
  • In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

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