• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• Journal of Engineering Education Research
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• v.6 no.2
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• pp.22-29
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• 2003

The ultimate goal of a hardware design course is to equip the students with the system design ability. However, the majority of the current structures of the design courses are focused on the understanding of the operational principles of each device which is used later as a building block for the design of a system. The shortcomings of this approach are, first, that it is very hard to keep the students motivated to the end of the course where system design concepts are dealt, and, second, the students do not have enough experience of the system design which is usually required in the field. As an alternative to solve these problems, it is necessary to reverse the order of contents of the course. Namely we introduce the high level of the abstract concept of the system design in the very beginning of the course and later by lowering the level of abstraction to the operational principle of the internal devices. In this paper, we propose a new top-down methodology for the introductory hardware design course of logic design, where the design expression and verification in the system-level are introduced first and then detail knowledge on each device is introduced later. Also, we report a case result from a student's working group as part of an extracurricular education in order to verify the validity of our proposed approach

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2127-2133
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• 2010

In this paper, we proposed an architecture for supporting sensor transparency in sensor node operating systems, design the standard APIs (Application Programming Interfaces) and sensor device abstraction to provide the sensor transparency and implemented the sensor transparency in the TinyOS, the most well known sensor node operating system. With the proposed sensor node operating system which can support the sensor transparency, application developers can develop the target applications independent to each sensor device by using the standard APIs provided by the sensor node operating system and the sensor device manufacturers also can develop sensor device drivers by using the standard hardware interfaces and HAL (Hardware Adaptation Layer) interfaces independent to the specific hardware platform of sensor nodes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.656-658
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• 2013

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of an elliptic curve crypto-engine server farm. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.177-182
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• 2010

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component in system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. In this paper, the implementation of a verification environment which is based on SystemC infrastructure and verifies the functionality of a hardware component is described. The proposed verification system uses SystemC user-defined channel as communication interface between variables of SystemC module and registers of Verilog module. The functional verification of an UART is performed on the proposed verification system. SystemC provides class library for hardware modeling and has an advantage of being able to design a system consisting hardware and software in higher abstraction level than register transfer level. Source codes of SystemC modules are reusable with a minor adaptation on verifying functionality of another hardware component.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.309-314
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• 2011

As a system becomes more complex, a design relies more heavily on a methodology based on high-level abstraction and functional verification. SystemVerilog includes characteristics of hardware design language and verification language in the form of extensions to the Verilog HDL. However, the OOP of System Veri log does not allow multiple inheritance. In this paper, we propose adoption of SystemC to introduce multiple inheritance. After being created, a SystemC unit is combined with a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes a design of a verification environment simple and easy through source code reuse. Moreover, a verification environment including SysemC unit has a benefit of reconfigurability due to OOP.

• Electronics and Telecommunications Trends
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• v.28 no.6
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• pp.13-27
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• 2013

SDN(Software Defined Network) 기술이 미국을 중심으로 먼저 출발하였으며 NFV(Network Function Virtualization) 기술은 유럽을 중심으로 한 SDN의 경쟁적인 기술로 초기에는 인식이 되었으나, 두 기술의 상호 시너지 효과를 고려하여 2013년 하반기부터는 다양한 형태의 협력 방안들이 표준단체, 산업체 및 캐리어들로부터 소개되고 있다. 두 기술이 지향하는 가장 큰 목표는 하드웨어의 의존성을 배제하고 네트워크 및 서비스를 추상화함으로써 캐리어들이 신규 서비스를 Time-to-Market에 맞게 그러면서도 유연하게 출시하고 제어 및 관리를 중앙집중 방식으로 제공하여 CAPEX(Capital Expenditure) & OPEX(Operating Expense)를 최소화 하는데 있다. 본고에서는 이 두 기술의 표준화 및 기술 동향, 그리고 아직은 태동기인 두 기술이 지향하는 다양한 Use Case들과 적용사례를 캐리어 환경 중심으로 살펴보고 향후 상용화 및 산업화에 대한 장 단기 발전 전망에 대해 기술 중심으로 예측해 본다.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06b
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• pp.114-116
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• 2012

본 논문에서는 대규모 무기체계에서 정보 모델 기반의 통합 관리 및 모니터링 시스템을 위한 결함허용 방법을 제시한다. 정보 모델 기반의 통합 관리 및 모니터링 시스템은 이기종 분산 환경으로 이루어지는 대규모 무기체계의 하드웨어 및 애플리케이션을 추상화된 정보 모델을 이용하여 관리할 수 있는 중앙 관리 및 통제 시스템이다. 대규모 무기체계에서는 하나의 시스템에서 오류가 발생하게 되면 시스템 전체에 영향을 줄 수 있기 때문에 중앙 관리 및 통제 시스템에서의 결함허용 방법이 필요하다. 이 문제를 해결하기 위해 정보 모델을 관리하기 위한 결함허용 그룹을 정의하고, 결함허용 그룹마다 서로 다른 결함허용 방법을 설정하여 애플리케이션의 중요도에 따라 다양한 방법을 이용하여 결함허용을 수행한다.

• Information and Communications Magazine
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• v.32 no.10
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• pp.49-57
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• 2015

클라우드 컴퓨팅이 확산되면서 핵심기술인 가상화 기술(Virtualization)에 관한 관심이 높아지고 있으며, 적용 범위도 단말기부터 서버, 네트워크까지ICT 인프라 전 분야로 확장되고 있다. 그러나, ICT인프라 자원의 가상화 구현을 위해서는 물리적 하드웨어 자원을 논리적으로 추상화하기 위해 하이퍼바이저 등의 새로운 가상화 계층을 구축할 수 밖에 없는데, 정보보호 측면에서 기존 보안기술이 모니터링할 수 없는 보안 사각지대가 되어 새로운 보안 취약성 및 공격경로를 발생 시킨다. 이러한 가상화 계층의 취약성분석 및 대응을 위한 관련 기술 개발 및 연구가 주목 받고 있다. 이에 본 고에서는 가상화 기술의 특성과 가상화 계층의 주요 보안위협 및 대응기술에 대해서 살펴 보고자 한다.

• 한국IT서비스학회:학술대회논문집
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• 2009.11a
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• pp.467-472
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• 2009

USN은 하드웨어와 유 무선 통신기술이 서로 네트워크로 연결되어 사물이나 환경의 정보를 획득하고 가공해 유용한 정보로 창출하는 것을 목표로 하고 있으며, 그 중 u-Healthcare는 의료 서비스 질 향상이라는 필요성에 의해 이슈가 되고 있다. 본 논문에서는 이 기종 센서 네트워크에서 획득한 데이터를 추상화하고 상황에 맞는 서비스를 제공하는 지능형 미들웨어를 설계하였다. 설계된 미들웨어를 사회적 이슈가 되고 있는 IT의료 분야에 적용해서 헬스 케어 모니터링 시스템을 구현했다. 센서를 통해 온도, 습도, 조도, 심박 수, 체온을 측정해서 실시간으로 관리하고 모니터링 하는 기능을 지원한다. 또한, 실시간으로 전달되는 바이오 정보를 통합 관리하는 부분에 초점을 맞추어 연구를 진행했다.