• 전자공학회논문지 IE
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• v.47 no.1
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• pp.48-55
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• 2010

The goal of this paper is to determine optimal hardware platform for specific applications. In order to develop an understanding of how select the optimal platform, we focus upon the real-time embedded vehicle system for processing forward image and sound. In this paper we propose to measure parameters such as instructions, execution cycle, required memory size for program and data by using ARMulator. We have measured three types of processor cores: ARM7, ARM9 and ARM10. The results of the study indicated that the proposed methods could measure the minimal requirements of hardware platform for specific applications. By defining lower limit of hardware specifications in embedded systems, we can minimize expenses with suitable system performance without implementing the system.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.7
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• pp.1031-1038
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• 2001

In order to verify the analytical methods predicting failure behavior of cracked piping, full-scale pipe tests are crucial in nuclear power plant piping. For this reason, series of international test programs have been conducted. However, full-scale pipe tests require expensive testing equipment and long period of testing time. The objective of this paper is to develop a test system which can economically simulate the full-scale pipe test regarding the integrity evaluation. This system provides the failure behavior of cracked pipe by testing a wide-plate specimen. The system provides the failure behavior of cracked pipe by testing a wide-plate specimen. The system was developed for the integrity evaluation of nuclear piping based on the methodology of hardware-in-the-loop (HiL) simulation. Using this simulator, the piping integrity can be evaluated based on the elastic-plastic behavior of full-scale pipe, and the high cost full-scale pipe test may be replaced with this economical system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.507-511
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• 2010

Digital Radio Frequency Memory (below, DRFM) performs RF signal data store, delay and re-transmission. DRFM is wildly used as core module of Jammer, EW simulator, Target Echo Generator etc. This paper suggests a hardware design of DRFM which is composed RF section(RF Input/Output Module, Local Oscillator Module) and Digital section(ADC module, memory, DAC module), and confirm the validity of the propose by the test result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1707-1721
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• 2004

In this paper, we propose a distributed communication model of intrusion detection system(IDS) in which integrated security management at networks level is possible, model it at a security node and distributed system levels, design and implement a simulator. At the node level, we evaluate the transfer capability of alert message based on the analysis of giga-bit security node architecture which performs hardware-based intrusion detection. At the distributed system level, we perform the evaluation of transfer capability of detection and alert informations between components of distributed IDS. In the proposed model, we carry out the performance evaluation considering decision factors of communication mechanism and present the results in order to gain some quantitative understanding of the system.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.24-26
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• 2015

최근 많이 활용되고 있는 라즈베리파이에 기반한 임베디드 시스템을 구축함에 있어서 사용자는 회로에 대한 이해와 하드웨어 비용이라는 측면에서 어려움을 갖게 되는 경우가 많다. 본 논문에서는 이러한 시스템을 가상으로 테스트할 수 있는 솔루션을 제안하고자 한다. 개발된 프로그램은 사용자가 실제 회로를 구성하는 것과 같이 가상의 공간에서 모듈을 배치하고 모듈 간에 선을 연결하는 것으로 회로를 구성하고 동작을 테스트할 수 있다 프로그램은 회로편집기, 인터프리터, 시뮬레이터의 세 가지 요소로 구성되어 있으며 전체 9개의 모듈을 제공하고 있다. 각각의 모듈은 제조사에서 제공하는 데이터 시트와 제원을 바탕으로 실제 회로 테스트를 거쳐 추상화하는 작업을 수행하였다. 개발된 프로그램의 품질수준을 한층 끌어올린다면 비용절감과 학습, 교육 측면에서 유용하게 이용될 수 있으며, 전기물리엔진의 구현, 실제 보드로 포팅이 가능한 수준의 인터프리터, 시뮬레이션 로직의 일반화가 필요할 것으로 판단된다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.82-94
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• 2015

In this paper, we propose hardware prefetch mechanism with an efficient cache replacement policy by giving priority to the trigger block in which a spatial region and producing a spatial region by using the displacement field. It could be taken into account the sequence of the program since a history is based on the trigger block of history record, and it could be quickly prefetching the instructions or data address by adding a stored value to the trigger address and displacement field since a history is stored as a displacement value. Also, we proposed a method of replacing at random by the cache replacement policy from the low priority block when the cache area is full after giving priority to the trigger block. We analyzed using the memory simulator program gem5 and PARSEC benchmark to assess the performance of the hardware prefetcher. As a result, compared to the existing hardware prefecture to generate the spatial region using a bit vector, L1 data cache miss rate was reduced about 44.5% on average and an average of 26.1% of L1 instruction misses occur. In addition, IPC (Instruction Per Cycle) showed an improvement of about 23.7% on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8B
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• pp.668-676
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• 2012

In this paper, on the assumption that MPI collective communication function is converted into a group of point-to-point communication functions in the transaction level, an algorithm that optimizes broadcast, scatter and gather function among MPI collective communication is proposed. The MPI hardware engine that operates the proposed algorithm was designed, and it was named the OCC-MPE (Optimized Collective Communication Message Passing Engine). The OCC-MPE operates point-to-point communication by using the standard send mode. The transmission order is arranged according to the algorithm that proposes the most frequently used broadcast, scatter and gather functions among the collective communications, so the whole communication time is reduced. To measure the performance of the proposed algorithm, the OCC-MPE with the Bus Functional Model (BFM) based on SystemC was designed. After evaluating the performance through the BFM based on SystemC, the proposed OCC-MPE is designed by using VerilogHDL. As a result of synthesizing with the TSMC $0.18{\mu}m$, the gate count of each OCC-MPE is approximately 1978.95 with four processing nodes. That occupies approximately 4.15% in the whole system, which means it takes up a relatively small amount. Improved performance is expected with relatively small amounts of area increase if the OCC-MPE operated by the proposed algorithm is added to the MPSoC (Multi-Processor System on a Chip).

• Journal of the Korea Society for Simulation
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• v.29 no.1
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• pp.39-46
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• 2020

The utilization of artificial intelligence (AI) in the engagement has been a key research topic in the defense field during the last decade. To pursue this utilization, it is imperative to acquire a realistic simulation to train an AI engagement agent with a synthetic, but realistic field. This paper is a case study of training an AI agent to operate with a hardware realism in the air-warfare dog-fighting. Particularly, this paper models the pursuit of an opponent in the dog-fighting setting with a gun-only engagement. In this context, the AI agent requires to make a decision on the pursuit style and intensity. We developed a realistic hardware simulator and trained the agent with a reinforcement learning. Our training shows a success resulting in a lead pursuit with a decreased engagement time and a high reward.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.6
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• pp.582-588
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• 2013

Solid Oxide Fuel Cell (SOFC) has been focused as a promising power source, which can replace a diesel engine regarding as major source of air pollution by the ship, due to high efficiency and eco-friendly. High operating temperature of SOFC is enable to secure of high efficiency, use various fuels and no need of high priced catalyst, but it may damage to components of SOFC. Therefore temperature control system has to be designed and validated before employing the fuel cell system for securing high efficiency and reliability. In this paper, instead of using typical method to validate performance of the controller, which consumes high cost and time, performance validation system using Hardware-in-the-loop simulation was developed and validated performence of the designed temperature controller for SOFC system.