• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.165-173
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• 2014

This paper presents a fast and high-quality haze removal method by the modification of the conventional transmission estimation process. In the conventional haze removal method, the halo and blocking artifacts arises while estimating the transmission. In order to effectively reduce the artifacts, the proposed method employs the maximum filter after the calculation of the dark channel. Because of the reduction of the artifacts, the proposed method can simplify the transmission refinement process without sacrificing the quality of the results: this paper proposes to use the single-channel guided filter instead of the multi-channel guided filter. The experimental results demonstrate that the quality of the dehazed results by the proposed transmission correction process is improved and the haze removal speed is increased by up to 59.6%, when compared to the conventional ones.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.93-99
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• 2017

In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.6
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• pp.741-747
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• 2012

In this paper, we propose a fast and robust framework for detecting and tracking multiple targets. The proposed system includes two modules: object detection module and object tracking module. In the detection module, we preprocess the input images frame by frame, such as gray and binarization. Next after extracting the foreground object from the input images, morphology technology is used to reduce noises in foreground images. We also use a block-based histogram analysis method to distinguish human and other objects. In the tracking module, color-based tracking algorithm and Kalman filter are used. After converting the RGB images into HSV images, the color-based tracking algorithm to track the multiple targets is used. Also, Kalman filter is proposed to track the object and to judge the occlusion of different objects. Finally, we show the effectiveness and the applicability of the proposed method through experiments.

• Journal of IKEEE
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• v.18 no.3
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• pp.383-391
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• 2014

In this paper, temperature, pressure and flow analysis system for testing a fuel filter of a diesel engine at the low-temperature environment in winter, is proposed. The light oil of diesel engine below a specific temperature is changed to the waxing materials like paraffin, and it prevents engine to start easily because of reducing fluidity. Thus, built-in block heater should be installed with fuel filter in order to solve this problem. And it is necessary to design evaluation system that can analyze the performance according to temperature, pressure and flow characteristics near fuel filter at a very low temperature. In this paper, we measured a physical quantity related to the performance of around the fuel filter using the proposed system, and analyzed their characteristics. Also the measured data is transferred to remote user by using a web server of embedded systems, and analyzed their conditions in remote place via web browser in order to know the operating status of fuel filter. We installed the proposed system in a small test chamber to verify the performance and took an experiment in normal temperature and very low temperature, and could obtain temperature, pressure and flow of near the fuel filter. As a result, the fuel flow could be improved during operation of the fuel heater.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.39-47
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• 2010

This paper proposes a fully-utilized block-based 2D DWT architecture, which consists of four 1D DWT filters with two-channel QMF PR Lattice structure. For 100% hardware utilization, we propose a new method which processes four input values at the same time. On the contrary to the image-based 2D DWT which requires large memories, we propose a block-based 2D DWT so that we only need 2MN-3N of storages, where M and N stand for filter lengths and width of the image respectively. Furthermore, the proposed architecture processes in horizontal and vertical directions simultaneously so that it computes the DWT for an $N{\times}N$ image within a period of $N^2(1-2^{-2J})/3$. Compared to existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rate. However, the proposed architecture may suffer from the long critical path delay due to the cascaded lattices in 1D DWT filters. This problem can be mitigated by applying the pipeline technique with maximum four level. The proposed architecture has been designed with VerilogHDL and synthesized using DongbuAnam $0.18{\mu}m$ standard cell.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.66-69
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• 2000

In this paper, we proposed a postprocessing algorithm for quantization effects reduction in block coded images using the block classification and adaptive filtering. The proposed method consists of classification, adaptive inter-block filtering, and intra-block filtering. First, each block is classified into one of seven classes based on the characteristics of 8${\times}$8 DCT coefficients. Then each block boundary is filtered by adaptive inter-block filters according to the block classification. Finally for blocks which are classified into edge block, intra-block filtering is peformed. Experimental results show that the proposed method gives better results than the conventional methods from both a subjective and an objective viewpoint.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.735-738
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• 2005

This paper presents an AMBA-based IP that can perform the deblocking filtering operations required in the H.264 video compression. The deblocking filter circuit was optimized for area and performance. The AHB wrapper was added to the circuit to interface with the AMBA-based platform. The AMBA-compliant operation of the proposed IP was verified on the platform board with Xilinx Virtex2 XC2V600 FPGA and ARM9 processor.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.113-116
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• 2001

제로트리 부호화 알고리즘 중 효율적이며 잘 알려진 SPIHT는 높은 메모리 요구로 인해 하드웨어 구현에 큰 어려움을 가지고 있다. 이 논문에서는 저 메모리 사용과 빠른 제로트리 부호화 알고리즘을 제안한다. 메모리를 줄이고 빠른 코딩을 위한 방법으로 다음 3가지를 사용한다. 첫 번째, 리프팅을 이용한 웨이블릿 변환은 기존의 필터뱅크 방식의 변환보다 저 메모리와 계산량의 감소를 가진다. 두 번째, 웨이블릿 변환된 계수들은 블럭으로 나누어져 각각 코딩된다. 여기서 블록은 제로트리 구조가 유지되는 STB(spatial tree-based block)이다. 세 번째, Wheeler 와 Pearlman이 제안한 NLS (no list SPIHT)를 이용한 부호화이다. NLS는 효율성에서 SPIHT와 거의 같으며 작고 고정된 메모리와 빠른 부호화 속도를 보여준다.

• Journal of Broadcast Engineering
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• v.14 no.4
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• pp.501-508
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• 2009

This paper proposes an efficient transform-domain noise reduction scheme in an H.264 video encoder, where the generalized Wiener filtering is performed in a quantization process by multiplying each transform block with its adaptive multiplication factor. In practice, the computational complexity of the proposed scheme is negligible by replacing the multiplication operation with a simple look-up table method. Also, experimental results show that the proposed scheme provides outstanding noise reduction performance in an H.264 video encoder.