• Title/Summary/Keyword: 플래서 설계

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Design of 6bit CMOS A/D Converter with Simplified S-R latch (단순화된 S-R 래치를 이용한 6비트 CMOS 플래쉬 A/D 변환기 설계)

  • Son, Young-Jun;Kim, Won;Yoon, Kwang-Sub
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.11C
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    • pp.963-969
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    • 2008
  • This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

A Study on Preform Design in Plane-Strain Forging (평면변형 단조에서의 예비성형체 설계에 관한 연구)

  • Lee, J.H.;Kang, K.;Bae, C.E.
    • Journal of Advanced Marine Engineering and Technology
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    • v.23 no.5
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    • pp.678-685
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    • 1999
  • A UBET program is developed for determining flash the optimum sizes of preform and initial billet in plane-strain closed-die forging. The program consists of forward and backward tracing processes. In the forward program, flash, die filling and forging load are predicted. In backward tracing process the optimum dimensions of initial billet and preform are determined from the final-shape data based on flash design. Experiments are carried out with pure plasticine billets ar room temperature. The theoretical predictions of forging load and flow pattern are in good agree-ment with the experimental results.

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Efficient Message Relaying Scheme for Heterogeneous Platoons (혼성플래툰을 위한 효율적 메시지 중계 기법)

  • Jeong, Dong Geun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.2
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    • pp.172-174
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    • 2016
  • In heterogeneous platoons, consisting of various size of vehicles, the signal from/to a small-size vehicle may be blocked by adjacent large-size ones. In this case, some vehicles in between the source and the destination should relay the messages. We design an efficient message relaying scheme for these platoons and evaluate its performance, taking the linear topology of platoons into account.

A Study on the Optimal Limit State Design of Reinforced Concrete Flat Slab-Column Structures (한계상태설계법(限界狀態設計法)에 의한 철근(鐵筋)콘크리트 플래트 슬라브형(型) 구조체(構造體)의 최적화(最適化)에 관한 연구(研究))

  • Park, Moon Ho
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.4 no.1
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    • pp.11-26
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    • 1984
  • The aim of this study is to establish a synthetical optimal method that simultaneously analyze and design reinforced concrete flat slab-column structures involving multi-constraints and multi-design variables. The variables adopted in this mathematical models consist of design variables including sectional sizes and steel areas of frames, and analysis variable of the ratio of bending moment redistribution. The cost function is taken as the objective function in the formulation of optimal problems. A number of constraint equations, involving the ultimate limit state and the serviceability limit state, is derived in accordance with BSI CP110 requirements on the basis of limit state design theory. Both objective function and constraint equations derived from design variables and an analysis variable generally become high degree nonlinear problems. Using SLP as an analytical method of nonlinear optimal problems, an optimal algorithm is developed so as to analyze and design the structures considered in this study. The developed algorithm is directly applied to a few reinforced concrete flat slab-column structures to assure the validity of it and the possibility of optimization From the research it is found that the algorithm developed in this study is applicable to the optimization of reinforced concrete flat slab column structures and it converges to a optimal solution with 4 to 6 iterations regardless of initial variables. The result shows that an economical design can be possible when compared with conventional designs. It is also found that considering the ratio of bending moment redistribution as a variable is reasonable. It has a great effect on the composition of optimal sections and the economy of structures.

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Design and Implementation of 2004 MX Flash Contents (2004 MX 플래시 컨텐츠 설계 및 구현)

  • Kim, Myeong-Se;Hong, Sung-Soo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.05a
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    • pp.131-134
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    • 2004
  • "사랑은 움직이는 거야" 라는 광고 문구를 보면서 움직임(애니메이션)이 얼마나 중요한가를 단적으로 알수 있다. 이동성이 현대 사회에서 강조되면서 움직임의 패러다임은 인터넷과 홈페이지의 개념을 바꿔 놓았다. 플래시는 이러한 움직임을 기본으로 하고 있다. 플래시의 최대 강점은 애니메이션이며, 애니메이션은 고도의 상품 개발 자유도를 가지고 있고, 감성과정서, 오락과 문화를 제공하는 정보기술 산업 및 영상미디어 문화 산업이다. 특히 온라인 네트웍크, 디카, 컬러폰의 대중화로 애니메이션, 게임 등 문화 컨텐츠를 쉽게 접근 할 수 있는 시대가 도래되었다. 이러한 필요성에 따라서 국내 대학에서는 이와 관련된 학과들이 수없이 많이 생겨나고 있으나 아직 플래시 애니메이션과 게임 제작에 대한 컨텐츠가 미비한 실정이다. 본 논문에서는 학생들이 쉽게 애니메이션과 게임을 제작할 수 있는 "MX 2004 위한 플래시 컨텐츠 제작" 모델을 제안하였다. 제안된 모델은 별도의 패키지 없이 간단하고 용이하게 사용될 수 있다. 전문가들을 위한 3D-MAX, 마야, VRML이 아니라 현재 일반 사용자들이 가장 많이 사용하고 있는 플래쉬를 이용하여 12가지 기본 방법을 제안하고 이를 게임과 애니메이션을 제작할 수 있는 제작방법 등을 수록한 모델을 설계하고 구현하였다.

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Design of a 6bit 800MS/s CMOS A/D Converter Using Synchronizable Error Correction Circuit (동기화 기능을 가지는 오차보정회로를 이용한 6비트 800MS/s CMOS A/D 변환기 설계)

  • Kim, Won;Seon, Jong-Kug;Yoon, Kwang-Sub
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.5A
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    • pp.504-512
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    • 2010
  • The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

Analysis Simultaneously Switching Density Using Ring Oscillator (Ring Oscillator를 이용한 신호의 동시 스위칭 밀도 분석)

  • Jeong, Sang-Nam;Baeg, Sang-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.9
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    • pp.79-84
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    • 2008
  • Switching speeds increase in both frequency and the transition rate of edges. Inadequate forecast for simultaneous switching signals may cause designing the power planes without sufficient current capability. The delay of critical signals in a chip can be therefore inadvertently increased and the situation makes it hard to debug issues. It is important to find the degree of increased switching during the debugging or chip characterization phases. This paper proposes the interpolation method to predict the switching density in a design. The interpolation was achieved by utilizing the dependencies between switching frequency and the delay appeared in a ring oscillator. The ring oscillator was primarily used to accumulate the effects of the ground bounce by higher switching. The result of interpolation was demonstrated using DongBu Hitec 0.18um CMOS technology.

Design of the Blade-Type Optical Bench for Earth Observation Satellite (지구관측위성의 블레이드형 광학탑재체 지지구조물 설계)

  • Kim, Kyung-Won;Kim, Jin-Hee;Rhee, Ju-Hun;Jin, Ik-Min;Kim, Jong-Wo;Park, Jong-Sung
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.33 no.11
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    • pp.88-94
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    • 2005
  • This paper is a study on the blade-type optical bench satisfying stiffness and thermal pointing error requirements for earth observation satellite. According to shape requirements, optical bench is designed. Because it does not satisfy the stiffness requirement, the stiffener is added on the outer/inner area of optical bench. But it does not meet the thermal pointing error requirement. So symmetrical structure is suggested with platform support structure attached on the upper/lower part of platform. Although it has better value than previous case, it still does not meet the thermal pointing error requirement. Based on the results of prior cases, optical bench finally designed, which satisfied both the stiffness and thermal pointing error requirements. Next conclusions follow from this design. It is efficient to increase thickness of platform facesheet, add stiffener and increase blade number to raise stiffness. It is effective to connect component consisting of same material and design optical bench having symmetrical structure to lower thermal pointing error.

A Study on Characteristics of Series-Fed Dipole Pair Antenna with End-Aligned Strip Pair Director (종단 정렬된 스트립 쌍 도파기를 가지는 직렬 급전 다이폴 쌍 안테나의 특성 연구)

  • Yeo, Junho;Lee, Jong-Ig;Park, Jin-Taek
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.4
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    • pp.805-810
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    • 2014
  • In this paper, the characteristics of a series-fed dipole pair antenna with an end-aligned strip pair director are studied. In the proposed SDP antenna, two strip dipole antennas with different lengths and a ground reflector are connected trough a coplanar stripline. The strip pair director placed above the second dipole element are two rectangular-shaped strips and is aligned at the ends of the two arms of the second dipole. The variations on the antenna performance for different lengths and widths of the director are analyzed, and optimal design parameters for the enhancement of the bandwidth are obtained. The optimized SDP antenna is fabricated on an FR4 substrate, and the experimental results show that the antenna has a frequency band of 1.65-2.95 GHz for a VSWR < 2, which shows enhanced bandwidth compared to the conventional SDP antenna.

Design of Double-Dipole Quasi-Yagi Antenna with 7 dBi gain (7 dBi 이득을 가지는 이중 다이폴 준-야기 안테나 설계)

  • Yeo, Junho;Lee, Jong-Ig;Baek, Woon-Seok
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.245-252
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    • 2016
  • In this paper, the design of a double-dipole quasi-Yagi antenna (DDQYA) with a gain over 7 dBi at 1.70-2.70 GHz band is studied. The proposed DDQYA consists of two strip dipoles with different lengths and a ground reflector, which are connected trough a coplanar stripline. The length of the second dipole is adjusted to increase the gain in the low frequency band, whereas a rectangular patch director is appended to the DDQYA to enhance the gain in the middle and high frequency band. The effects of the length of the second dipole, and the length and width of the director on the antenna performance are analyzed, and final design parameters to obtain a gain over 7 dBi are obtained. A prototype of the proposed DDQYA is fabricated on an FR4 substrate, and the experimental results show that the antenna has a frequency band of 1.60-2.86 GHz for a VSWR < 2, and measured gain ranges 7.2-7.6 dBi at 1.70-2.70 GHz band.