• Journal of KIISE:Software and Applications
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• v.28 no.3
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• pp.211-223
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• 2001

본 논문에서 제안하는 시나리오기반 검증기법의 목적은 UML로 작성된 객체지향 분석모델의 완전성 및 일관성을 진단하는 것이다. 검증기법의 전체 절차는 요구분석을 위한 Use Case 모델링 과정에서 생성되는 Use Case 시나리오와 UML 분석모델로부터 역공학적 방법으로 도출된 객체행위 시나리오와의 상호참조과정 및 시나리오 정보트리 추적과정을 이용하여 단계적으로 수행된다. 본 검증절차를 위하여 우선, UML로 작성된 객체지향 분석모델들은 우선 정형명세언어를 사용하여 Use Case 정형명세로 변환하다. 그 다음에, Use Case 정형명세로부터 해당 Use Case 내의 객체의 정적구조를 표현하는 시나리오 정보트리를 구축하고, Use Case 정형명세 내에 포함되어 있는 객체 동적행위 정보인 메시지 순차에 따라 개별 시나리오흐름을 시나리오 정보트리에 표현한다. 마지막으로 시나리오 정보트리 추적과 시나리오 정보 테이블 참조과정을 중심으로 완전성 및 일관성 검증작업을 수행한다. 즉, 검증하고자 하는 해당 Use Case의 시나리오 정보트리를 이용한 시나리오 추적과정을 통해 생성되는 객체행위 시나리오와 요구분석 과정에서 도출되는 Use Case 시나리오와의 일치여부를 조사하여 분석모델과 사용자 요구사양과의 완전성을 검사한다. 그리고, 시나리오 추적과정을 통해 수집되는 시나리오 관련종보들을 가지고 시나리오 정보 테이블을 작성한 후, 분석과정에서 작성된 클래스 관련정보들의 시나리오 포함 여부를 확인하여 분석모델의 일관성을 검사한다. 한편, 본 논문에서 제안하는 검증기법의 효용성을 증명하기 위해 대학의 수강등록시스템 개발을 위해 UML을 이용해 작성된 분석모델을 특정한 사례로써 적용하여 보았다. 프로세싱 오버헤드 및 메모리와 대역폭 요구량 측면에서 MARS 모델보다 유리함을 알 수 있었다.과는 본 논문에서 제안된 프리페칭 기법이 효율적으로 peak bandwidth를 줄일 수 있다는 것을 나타낸다.ore complicate such a prediction. Although these overestimation sources have been attacked in many existing analysis techniques, we cannot find in the literature any description about questions like which one is most important. Thus, in this paper, we quantitatively analyze the impacts of overestimation sources on the accuracy of the worst case timing analysis. Using the results, we can identify dominant overestimation sources that should be analyzed more accurately to get tighter WCET estimations. To make our method independent of any existing analysis techniques, we use simulation based methodology. We have implemented a MIPS R3000 simulator equipped with several switches, each of which determines the accuracy level of the

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1899-1909
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• 2007

A cross-coupled charge pump with internal pumping capacitor, witch is advantages from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using a NMOS and a PMOS diode connected to boosting node from VIN node, the pumping node is precharged to the same value each pumping node at start pumping operation. Since the lust-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located the font side of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with conventional cross-coupled charge pump by using a stack-MIM capacitors. A proposed charge pump for TFT-LCD driver IC is designed with $0.13{\mu}m$ triple-well DDI process, fabricated, and tested.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.184-192
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• 2019

Compared to 31-mode rings, 33-mode rings are highly utilized as wide bandwidth underwater acoustic transducers because the electro-mechanical coupling and piezoelectric constant d are high. On the other hand, the 31-mode ring is an axial symmetry structure, so it is possible to model it as a simple two-dimensional asymmetrical model for numerical analysis, but the 33-mode ring requires a three-dimensional numerical analysis. That is, a lot of computing resources and computation time are required. In this study, the effective material properties of an equivalent 31-mode ring were derived to simulate the electro-mechano-acoustical responses of the 33-mode ring transducer. Using the effective material properties derived from this study, a numerical analysis of rings in vacuum, air backed rings in water, and FFR (Free Flooded Ring) transducers were performed to compare the responses of 33-mode rings.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).