• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.499-500
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• 2008

기존 칩들 사이에 사용되는 인터페이스는 많은 선을 사용하여 EMI문제를 발생시키고 PCB에 많은 중간을 차지한다. 이를 해결하기 위하여 개발된 UniPro는 적은 선으로 빠른 통신속도를 지원하며 저전력 통신을 위하여 D-PHY와 함께 사용된다. 본 논문에서는 MIPI 규격의 UniPro를 설계하였다. 설계된 UniPro는 4개의 데이터 레인과 1개의 클럭 레인으로 구성하여 디바이스 사이의 데이터 및 제어신호를 전송 가능하다. 또한 낮은 전력소모를 위하여 전원 관리 장치를 추가하였으며 수신한 데이터의 에러검출이 가능하도록 설계하여 신뢰도를 높였다. 설계된 인터페이스는 5,160 Gate크기이며 속도는 98MHz이다.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.47-54
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for imbedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro)-TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter-TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• Journal of IKEEE
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• v.15 no.4
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• pp.345-353
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• 2011

Recently portable mobile devices such as smart-phones and notebooks have rapidly increasing demands. Those devices consume more power because they are expected to offer more complex functionality including multimedia features. For these reasons engineering efforts are changing to focus on maximizing energy efficiency within a limited battery capacity instead of increasing computational performance. In this paper, we propose a battery management system using event driven programming technique on a embedded processor. We also show that the proposed system satisfies SBS (Smart Battery Specification) v1.1. The proposed system maintains minimum code size and memory size comparing to those of RTOSs. The proposed system can be also easily incorporated in the conventional RTOSs as a form of firmware.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10b
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• pp.262-264
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• 2003

다목적실용위성 2호에 탑재 되어 있는 탑재소프트웨어는 위성의 자세, 전력, 열 제어 및 지상 명령 수신, 측정 데이터 수집 등 여러 개의 소프트웨어 모듈로 구성되어 있으며, 각 소프트웨어 모듈은 실시간 운용체제인 VRTX에 의해서 제어된다. 다목적실용위성 2호에서 사용하는 탑재소프트웨어는 일반적인 소프트웨어와 달리 고도의 신뢰성과 안정성을 보장해야 하며 지상과의 통신이 없는 상태에서도 위성을 정상적으로 운용할 수 있어야 하며, 위성 시스템의 장애가 발생시 위성을 안전 모드로 전환 할 수 있어야한다. 본 논문에서는 다중프로세서 구조를 갖는 다목적실용위성 2호의 탑재소프트웨어 초기화 및 태스크를 관리하며 위성의 Health 관리를 담당하는 Executive CSC(Computer Software Component)의 설계와 구현에 대하여 설명한다.

• Annual Conference of KIPS
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• 2012.04a
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• pp.1171-1173
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• 2012

이제는 하나뿐인 지구를 지키고 살리는 녹색혁명의 시대에 살고 있다. 이에 따라 컴퓨팅의 환경도 그린 컴퓨팅 환경으로 바뀌어지고 있다. 그린 컴퓨팅은 컴퓨팅 작업에 소모되는 에너지를 줄여보자는 것으로서 컴퓨터에 대한 전력을 절감함으로써 에너지 비용 절감, 저탄소 환경으로 구성하는 것이다. 그린 컴퓨팅은 녹색 ICT(Information ＆ Communication Technology)의 일환으로, 컴퓨터 자체를 움직이는 여러 에너지들 뿐만 아니라 컴퓨터의 냉각과 구동 및 주변기가들을 작동시키는데 소모되는 전력 등을 줄이기 위해서 CPU나 GPU등 각종 프로세서들의 재설계, 대체에너지 등을 활용하는 방안 등 탄소배출을 최소화시키는 등의 환경을 보호하는 개념의 컴퓨팅이다. Christian Belady 2007년 2월, Electronics Cooling Magazine의 통계에 의하면 2001년에는 인프라 비용과 전력 비용의 합이 서버의 가격과 같았고, 2004년에는 인프라 비용이 서버 비용과 같아졌다. 그런데, 2008년에는 에너지 비용 하나만으로도 서버 비용과 같아졌다는 것을 알 수 있습니다. 이제 그린 IT, 그린 컴퓨팅은 하면 좋고, 안하고 말고가 아닌 하지 않으면 생존할 수 없는 필수적인 것으로 되어가고 있다. 본 논문에서는 KISTI 슈퍼컴퓨터에서의 그린 컴퓨팅을 구현하기 위하여 먼저 이를 적용하기 위한 서버 시스템을 설계 구축하고 각각의 프로그램을 개발하여 테스트하였다.

• Journal of the Korea Society of Computer and Information
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• v.12 no.5
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• pp.103-112
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• 2007

In this paper, we implement a hypervisor that runs multiple uC/OS-II real-time kernels on one microprocessor. The hypervisor virtualizes microprocessor and memory that are main resources managed by uC/OS-II kernel. Microprocessor is virtualized by controlling interrupts that uC/OS-II real-time kernel handles and memory is virtualized by partitioning physical memory. The hypervisor consists of three components: interrupt control routines that virtualize timer interrupt and software interrupt, a startup code that initializes the hypervisor and uC/OS-II kernels, and an API that provides communication between two kernels. The original uC/OS-II kernel needs to be modified slightly in source-code level to run on the hypervisor. We performed a real-time test and an independent computation test on Jupiter 32-bit EISC microprocessor and showed that the virtualized kernels run without problem. The result of our research can reduce the hardware cost, the system space and weight, and system power consumption when the hypervisor is applied in embedded applications that require many embedded microprocessors.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.5
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• pp.11-19
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• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• Journal of Digital Convergence
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• v.13 no.8
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• pp.245-251
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• 2015

If a digital signage system is operated in PC mounted in the Window OS then the implementing price is very high. For resolving this problem, we used the Smartphone mounted in ARM Cortex family of multi-core processor-based mobile platform. We developed a low-power low-cost digital signage system and a remote convergence content management program based on web server. This convergence system manages advertising content to a remote control device anywhere using remote control technology. This system is one integrated system with display and is a low-power consumed and is developed in very efficient hardware interface. And condition sensors(intensity of illumination, temperature, weather, GPS etc) is equipped in the developed system. Automatic contents builder and Context-aware SMIL module is also implemented in the convergence system. We achieved over 50% power savings comparing with conventional Window OS system and 16 points multi-touch in our system.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.10
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• pp.59-65
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• 2007

Recently, ubiquitous sensor network(USN) techniques have been applied to electric power facility management. This paper dealt with the designed and fabricated ubiquitous sensors which monitor transformers and lightning arresters installed in overhead distribution systems. The sensors consist of a 8-[bit] microprocessor unit, a wireless communication nodule specified in IEEE 802.15.4, and associated electronics. A Rogowski coil was fabricated to measure load of transformer and surge current without saturation having good linearity up to 1000[A]. A zero-phase current transformer with a high relative permeability of $10^5$ at 180[Hz] was used to detect small leakage current of $50[{\mu}A]{\sim}1[mA]$ flowing lightning arrester, and the frequency bandwidth of the module is ranges from 12[Hz] to 1.24[kHz] at -3[dB].

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.1-8
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• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.