• The Journal of the Convergence on Culture Technology
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• v.4 no.3
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• pp.287-291
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• 2018

The CNTFET, which is attracting attention as a next-generation semiconductor device, can obtain ballistic or near-ballistic transport at a lower voltage than that of conventional MOSFETs by depositing CNTs between the source and drain of the device. In order to increase the performance of the CNTFET, a large number of CNTs must be deposited at a high density in the CNTFET. Thus, various manufacturing processes to increase the density of the CNTs have been developed. Recently, the Directional Shrinking Transfer Method was developed and showed that the current density of the CNTFET device could be increased up to 150 uA/um. So, this method enhances the possibility of implementing a CNTFET-based integrated circuit. In this paper, we will discuss how to evaluate the performance of the CNTFET device compared to a MOSFET at the circuit level when the CNTFET is fabricated by the Directional Shrinkage Transfer Method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.269-275
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• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.140-140
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• 2016

유기전계발광소자 (Organic Light Emitting Diode : OLED)는 보조광원이 필요 없고 천연색 표현이 가능하며, 낮은 소비 전력 및 저전압 구동 등의 장점으로 이상적인 디스플레이 구현이 가능하여 차세대 디스플레이로써 많은 이목을 끌고 있으나 제한된 수명과 안정성의 문제점을 안고 있다. 따라서 OLED의 열화 원인을 분석하고 수명을 연장하기 위한 체계적인 방법과 기술 개발이 중요하다. Impedance Spectroscopy는 이온, 반도체, 절연체 등의 벌크 또는 계면 영역의 전하 이동을 조사하는데 사용될 수 있어, OLED에서도 Impedance Spectroscopy를 이용하여 전하수송과 전자주입 메커니즘 등 폭넓은 전기적 정보를 얻을 수 있다. 본 연구에서는 Impedance Spectroscopy를 이용하여 경과시간에 따른 OLED의 임피던스 특성을 측정하여 열화 메커니즘을 분석하였다. 본 연구에서 OLED는 ITO / 2-TNATA (4,4,4-tris2-naphthylphenyl-aminotriphenylamine) / NPB (N,N'-bis-(1-naphyl)-N, N'-diphenyl-1,1'- biphenyl-4,4'-diamine) / Alq3 (tris(quinolin-8-olato) aluminum) / Liq / Al으로 구성된 녹색 형광 OLED를 제작하였다. OLED의 전계 발광 특성을 측정하기 위한 전원 인가장치로 Keithley 2400을 사용하여 전압과 전류를 인가하였고, 소자에서 발광된 휘도 및 발광 스펙트럼은 Photo Research사의 PR-650 Spectrascan을 사용하여 암실 환경에서 측정하였다. 임피던스 스펙트럼은 컴퓨터 제어 프로그래밍이 가능한 KEYSIGHT사의 E4990A를 사용하여 측정하였다. 임피던스 측정 전압은 0 V부터 2 V 간격으로 8 V까지, 주파수는 20 Hz에서 2 kHz의 범위로 설정하여 측정하였다. I-V-L과 임피던스 특성은 24 시간의 간격을 두고 실온에서 측정하였다. 그림은 경과시간에 따른 녹색 형광 OLED의 인가전압 2 V, 6 V의 Cole-Cole plot을 나타낸 것이다. 문턱전압 미만인 인가전압 2 V에서는 소자를 통하여 전류가 흐르지 않아 큰 반원 형태를 나타내었고, 시간이 경과함에 따라 소자 제작 직후엔 실수 임피던스의 최댓값이 $8982.6{\Omega}$에서 480 시간 경과 후엔 $9840{\Omega}$으로 약간 증가하였다. 문턱전압 이상인 인가전압 6 V에서는 소자 제작 직후 실수 임피던스의 최댓값이 $108.2{\Omega}$으로 작은 반원 형태를 나타내나 시간이 경과함에 따라 방사형으로 증가하는 것을 확인 할 수 있었고, 672 시간 경과 후엔 실수 임피던스의 최댓값이 $9126.9{\Omega}$으로 문턱 전압 미만 일 때와 유사한 결과를 나타내었다. 이러한 임피던스의 증가 현상은 시간이 경과함에 따라 OLED의 열화에 의한 것으로 판단된다.

• Journal of Aerospace System Engineering
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• v.16 no.4
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• pp.10-16
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• 2022

Since aviation systems are developed as the complex form of software a hardware, the necessity to apply to relevant guidelines is increasing. It is however uncommon that international development guidelines regarding electronic hardware are applied to current domestic aviation systems. In this paper, we compare and analyze DO-254 and ECSS-Q-ST-60-02C, electronic hardware development guidelines with the case of KASS (Korea Augmentation Satellite System) Performance Suitability, based on the project of SBAS (Satellite Based Augmentation System) development and construction.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.90-100
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• 2011

We present a parallel bi-conjugate gradient (Bi-CG) matrix solver for large scale Bio-FET simulations based on recent graphics processing units (GPUs) which can realize a large-scale parallel processing with very low cost. The proposed method is focused on solving the Poisson equation in a parallel way, which requires massive computational resources in not only semiconductor simulation, but also other various fields including computational fluid dynamics and heat transfer simulations. As a result, our solver is around 30 times faster than those with traditional methods based on single core CPU systems in solving the Possion equation in a 3D FDM (Finite Difference Method) scheme. The proposed method is implemented and tested based on NVIDIA's CUDA (Compute Unified Device Architecture) environment which enables general purpose parallel processing in GPUs. Unlike other similar GPU-based approaches which apply usually 32-bit single-precision floating point arithmetics, we use 64-bit double-precision operations for better convergence. Applications on the CUDA platform are rather easy to implement but very hard to get optimized performances. In this regard, we also discuss the optimization strategy of the proposed method.