• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1849-1854
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• 2010

As for information system in hospital which digital hospital aims at, there are PACS(Picture Archiving and Communication System) and soon. PACS transfer and store various medical pictures which are occurring in hospital. The various medical pictures is captured by using keyboard or foot switch during a surgical operation. In this paper, foot switch USB module that can be mounted into a main foot switch case is designed and implemented, it is having a MCU circuit with a built-in micro-controller and a I/O interface having a maximum of five switch. we also developed foot switch control software program with various functions. The result of using the module in the hospital field confirms that the module operates safely.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.254-256
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• 2000

본 논문에서는 여러 단계의 QoS(Quality of Service)를 지원하면서 빠르고 확장이 용이하며 각종 패킷 폐기(packet drop) 방식을 지원하는 평형 파이프라인 우선순위 아웃풋 큐 구조(balanced pipelined priority output queue architecture)를 제시하고 있다. 본 방안은 기존에 연구된 파이프라인 우선순위 힙(pipelined heap, P-heap)[1]을 기반으로 하고 있다. 파이프라인 우선순휘 힙은 우선순위에 따라 패킷을 전송하는 작업을 파이프라인 방식으로 처리하여 처리 성능을 향상시킨 아웃풋 큐 구조이다. 그러나 P-heap은 평형성(balance) 문제를 전혀 고려하고 있지 않으며, 다양한 패킷 폐기 방안을 제공하고 있지 못하다. 본 논문에서는 이런 측면에서 P-heap을 개선한 Advanced P-heap을 제안하고 있다. Advanced P-heap은 평균적인 상황에서 힙에 평형성을 부여하고, 각종 패킷 폐기 정책을 지원할 수 있는 일반적인 우선순위별 차별 패킷 구조를 제시하고 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1393-1398
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• 2003

In this paper, we propose a new switch architecture with one schedule at k-time slots, which k means the allocated time slots for each schedule. A conventional switch system uses a single time slot per each schedule but the proposed switch system uses multiple time slots per each schedule. Both the conventional switch md the proposed switch have same throughput but our switch system occupies multiple cell time slots per each schedule and hence can be implemented in scheduler of simple circuitry compared to the conventional switch. The proposed scheduling method for switch system will be applicable in switch system with high-speed data link rate.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.52-63
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• 1998

In this paper, several improvements to a copy network proposed previously for multicast packet switching are described. The improvements provide a solution to some problems inherent in multicasting. The input fairness problem caused by overf low is solved by a dynamic starting point decider(DSD), which can calculate running sums of copy requests starting from any input port. The starting point is changed adaptively in every time slot based on both the fill level of the input buffers in current time slot and the overflow situations of the previous time slot. Using the fill level of the conventional network. The DSD also provides the function of regulating overall copy requests according to the amount of input traffics. This is an essential function in improving overall throughputs of the copy networks. The throughput of a multicast switch can be improved substantially if partial service of copy request is implemented when overflow occurs. Call-splitting can also be implemented by the DSD in a straightforward manner. The hardware for the DSD is derived with the objective of simple architectures for the high speed operation. Simulation study of the copy network under various traffic conditions is presented to evaluate its performance.

• The Journal of the Korea Contents Association
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• v.5 no.3
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• pp.217-225
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• 2005

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbitrates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides $100\%$ throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.629-637
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• 2006

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbirates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides 100% throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching. The proposed scheduling algorithm was implemented in FPGA and verified on board-level.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1124-1131
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• 2002

The banyan network is a popular and basic structure of the multi-stage ATM switches. This paper presents a novel approach to resolve the internal blocking of the banyan network by using a Non-Blocking Permutation Generator (NBPG). The NBPG performs two functions, i.e., the first is to extract the conflict cells from the incoming cells and Ole second is to re-assign new input port addresses to the conflict cells. As a result, NBPG generates non-blocking I/O permutations. To estimate the performance of the NBPG, we provide the results of several simulations.

• The Journal of the Acoustical Society of Korea
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• v.21 no.2
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• pp.128-133
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• 2002

We developed a electronic music glove (BMG) system that plays musical scores in real time processing. The EMG system interfaces with the signal coming from the controller to the sound card in the computer, The computer, according to the status of the fingers and foot switches, generates the sound signals and sends them to the speaker systems through the application C++ program and MIDI message. The EMG systems control the velocity and duration of sound and several musical performance expressions such as chorus, reverberation, rhythm, and volume. Finally, we implemented the digital drum set using: the EMG system as example.