• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.107-110
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• 2005

몰딩 공정중에 발생된 보이드(void)는 제품의 기계적인 물성치에 큰 영향을 준다. 미세균열(micro crack)이나 박리(delamination)등의 결함을 유발하는 보이드의 형성을 최소화시킬 수 있는 방법으로 진공 몰드를 제시하였다. 본 연구에서는 대기압 상태와 진공 상태에서 나타나는 유동 선단에서의 보이드 생성과 소멸을 실험관찰 하였고 몰드 패키지의 현상을 실험적으로 비교하였다. 아울러 진공 몰드의 공정 이론과 조건을 구하였다.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Journal of the Korean Society for Nondestructive Testing
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• v.19 no.5
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• pp.369-377
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• 1999

Recently, it is gradually raised necessity that thickness of thin film is measured accuracy and managed in industrial circles and medical world. Ultrasonic signal processing method is likely to become a very powerful method for NDE method of detection of microdefects and thickness measurement of thin film below the limit of ultrasonic distance resolution in the opaque materials, provides useful information that cannot be obtained by a conventional measuring system. In the present research. considering a thin film below the limit of ultrasonic distance resolution sandwiched between three substances as acoustical analysis model, demonstrated the usefulness of ultrasonic signal processing technique using information of ultrasonic frequency for NDE of measurements of thin film thickness. Accordingly, for the detection of delamination between the junction condition of boundary microdefect of thin film sandwiched between three substances the results from digital image processing.

• Tunnel and Underground Space
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• v.13 no.6
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• pp.465-475
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• 2003

Groundwater inflow into the caverns constructed in fractured rock mass was simulated by numerical modeling, NAPSAC (DFN, discrete fracture network model) and NAMMU (CPM, continuous porous media model), a finite-element software package for groundwater flow in 3D fractured media developed by AEA Technology, UK. The input parameters for modeling were determined on surface fracture survey, core logging and single hole hydraulic test data. In order to predict the groundwater inflow more accurately, the anisotropic hydraulic conductivity was considered. The anisotropic hydraulic conductivities were calculated from the fracture network properties. With a minor adjustment during model calibration, the numerical modeling is able to reproduce reasonably groundwater inflows into cavern and the travel length and times to the ground surface along the flow paths in the normal, dry and rainy seasons.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1673-1678
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• 2007

The use of flip-chip type electronic package offers numerous advantages such as reduced thickness, improved environmental compatibility, and downed cost. Despite numerous benefits, flip-chip type packages bare several reliability problems. The most critical issue among them is their electrical performance deterioration upon consecutive thermal cycles attributed to gradual delamination growth through chip and adhesive film interface induced by CTE mismatch driven shear and peel stresses. The electronic package in use is heated continuously by itself. When the crack at a weak site of the electronic package occurs, thermal deformationon the chip side is changed. Therefore, we can measure these micro deformations by using Moire interferometry and find out the crack length.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.89-93
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• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.

• Journal of Welding and Joining
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• v.16 no.4
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• pp.92-97
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• 1998

Because of the low melting temperature of solder, each temperature cycle initiates an irrecoverable creep deformation at the solder interconnection which connects the package body with the PCB. The crack starts and propagates from the position where the creep deformation is maximized. This work has tried to compare and analyze the thermal fatigue life of solder interconnection which is affected by the lead material, the size of die pad, chip thickness, and interface delamination of 48-Pin TSOP under the temperature cycle ($0^{\circ}C$~1$25^{\circ}C$). The crack initiation position and thermal fatigue life which are calculated by using FEA method are well matched with the results of experiments. The thermal Fatigue life of copper lead frame is extended around 3.6 times longer than that of alloy 42 lead frame. It is maximized when the chip size is matched with the length of the lead. It tends to be extended as the thickness of chip got thinner. As the interfacial delamination between die pad and EMC is increased, the thermal fatigue life tends to decrease in the beginning of delamination, and increase after the delamination grew after 45% of the length of die pad.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.31-36
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• 2002

The 2nd level solder joint reliability of 153 FC-BGA for high-speed SRAM (Static Random Access Memory) with the large chip on laminate substrate comparing to PBGA(Plastic Ball Grid Array) was studied in this paper. This work has been done to understand an influence as the mounting with single side or double sides, structure of package, properties of underfill, properties and thickness of substrate and size of solder ball on the thermal cycling test. It was confirmed that thickness of BT(bismaleimide tiazine) substrate increased from 0.95 mm to 1.20 mm and solder joint fatigue life improved about 30% in the underfill with the low young's modulus. And resistance against the solder ball crack became twice with an increase of the solder ball size from 0.76 mm to 0.89 mm in solder joints.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.59-62
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• 2013

Experimental analyses on the solder joint reliability of plastic ball grid array under harsh random vibration were presented. The chips were assembled on the daisy chained circuit boards for the test samples preparation, half of which were processed for underfill to investigate the underfill effects on the solder failures. Acceptance and qualification levels were applied for the solder failure tests, and the overall controlled RMS of the power spectrum densities of the steps were 22.7 Grms and 32.1 Grms, respectively. It was found that the samples survived without any solder failure during the tests, demonstrating the robustness of the packaging structure for potential avionics and space applications.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.19-27
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• 2003

Surface finishes of PCB laminates are important in the solder joint reliability of flip chip package because the types and thicknesses of intermetallic compound(IMC), and compositions and hardness of solders are affected by them. In this study, effects of surface finishes of PCB on the low cycle fatigue resistance of Sn-based lead-free solders; Sn-3.5Ag, Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag-XBi(X=2.5, 7.5) and Sn-0.7Cu were investigated for the Cu and Au/Ni surface finish treatments. Displacement controlled room temperature lap shear fatigue tests showed that fatigue resistance of Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag and Sn-0.7Cu alloys were more or less the same each other but much better than that of Bi containing alloys regardless of the surface finish layer used. In general, solder joints on the Au/Ni finish showed better fatigue resistance than those on the Cu finish. Cross-sectional fractography revealed microcracks nucleation inside of the interfacial IMC near the solder mask edge, more frequently on the Cu than the Au/Ni surface finish. Macro cracks followed the solder/IMC interface in the Bi containing alloys, while they propagated in the solder matrix in other alloys. It was ascribed to the Bi segregation at the solder/IMC interface and the solid solution hardening effect of Bi in the $\beta-Sn$ matrix.