• Title/Summary/Keyword: 패리티 비트

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Design of a Low-Power LDPC Decoder by Reducing Decoding Iterations (반복 복호 횟수 감소를 통한 저전력 LDPC 복호기 설계)

  • Lee, Jun-Ho;Park, Chang-Soo;Hwang, Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.9C
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    • pp.801-809
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    • 2007
  • LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

The performance analysis of a novel enhanced turbo coded system with increased time diversity effect (시간 다이버시티 효과를 증대시키는 새로운 ETD-터보 코드 적용시스템의 성능분석)

  • 고연화;하덕호
    • Journal of the Institute of Convergence Signal Processing
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    • v.4 no.4
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    • pp.73-80
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    • 2003
  • In this paper, we propose a ETD-turbo code(Enhanced Time Diversity turbo code) which is a novel turbo code configuration to increase the time diversity effect and analyze the performance of ETD-turbo coded MC-CDMA system. The ETD-turbo code, which is added another interleaver to the conventional turbo code structure, is consisted. Time diversity effect of the ETD-turbo code is improved by every parity bits converted into interleaver pattern. In order to the performance of the ETD-turbo code, we conduct a computer simulation about interleaver type. And we make comparison between the performance of ETD-turbo coded MC-CDMA system and the conventional turbo coded MC-CDMA system. By the simulation results, ETD-turbo code has less BER than the conventional turbo code and time delay is decreased by reducing iteration numbers. Therefore, it is defined that the performance of ETD-turbo coded MC-CDMA system is improved than the conventional turbo coded MC-CDMA system.

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Improved Correlation Noise Modeling for Transform-Domain Wyner-Ziv Coding (변환영역에서의 Wyner-Ziv 코딩을 위한 개선된 상관 잡음 모델)

  • Kim, Byung-Hee;Ko, Bong-Hyuck;Jeon, Byeung-Woo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2008.11a
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    • pp.81-84
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    • 2008
  • 최근 센서네트워크와 같은 에너지 제한 환경을 위한 경량화 부호화 기술의 필요성이 대두됨에 따라 분산 소스 부호화 기술(Distributed Source Coding)의 응용기술로 비디오 부호화 복잡도의 대부분을 차지하는 움직임 예측/보상과정을 부호화기가 아닌 복호화기에서 수행하는 분산 비디오 부호화 기술(Distributed Video Coding)에 대한 연구가 활발히 이루어져 왔다. 이에 가장 대표적인 기술인 Wyner-Ziv 코딩 기술은 채널 코드를 이용하여 원본 프레임과 이에 대한 복호화기의 예측영상인 보조정보 사이의 잡음을 제거하여 영상을 복원한다. 일반적으로 보조정보는 원본영상에 유사한 키 프레임간의 프레임 보간을 통하여 생성되며 채널 코드는 Shannon limit에 근접한 성능을 보이는 Turbo 코드나 LDPC 코드가 사용된다. 이와 같은 채널 코드의 복호화는 채널 잡음 모델에 기반하여 수행되어지며 Wyner-Ziv 코딩 기술에서는 이 채널 잡음 모델을 '상관 잡음 모델' (Correlation Noise Modeling)이라 하고 일반적으로 Laplacian이나 Gaussian으로 모델화 한다. 하지만 복호화기에는 원본 영상에 대한 정보가 없기 때문에 정확한 상관 잡음 모델을 알 수 없으며 잡음 모델에 대한 예측의 부정확성은 잡음 제거를 위한 패리티 비트의 증가를 야기해 부호화 기술의 압축 성능 저하를 가져온다. 이에 본 논문은 원본 프레임과 보조정보 사이의 잡음을 정확하게 예측하여 잡음을 정정할 수 있는 향상된 상관 잡음 모델을 제안한다. 제안 방법은 잘못된 잡음 예측에 의해 Laplacian 계수가 너무 커지는 것을 방지하면서 영상내의 잡음의 유무에 별다른 영향을 받지 않는 새로운 문턱값을 사용한다. 다양한 영상에 대한 제안 방법의 실험 결과는 평균적으로 약 0.35dB에 해당하는 율-왜곡 성능 향상을 보여주었다.

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A LDPC decoder supporting multiple block lengths and code rates of IEEE 802.11n (다중 블록길이와 부호율을 지원하는 IEEE 802.11n용 LDPC 복호기)

  • Na, Young-Heon;Park, Hae-Won;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.6
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    • pp.1355-1362
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    • 2011
  • This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

The Design and Implementation of Outer Encoder/Decoder for Terrestrial DMB (지상파 DMB용 Outer 인코더/리코더의 설계 및 구현)

  • Won, Ji-Yeon; Lee, Jae-Heung;Kim, Gun
    • The KIPS Transactions:PartA
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    • v.11A no.1
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    • pp.81-88
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    • 2004
  • In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

A Design of LDPC Decoder for IEEE 802.11n Wireless LAN (IEEE 802.11n 무선 랜 표준용 LDPC 복호기 설계)

  • Jung, Sang-Hyeok;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.5
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    • pp.31-40
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    • 2010
  • This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

A Cooperative Hybrid ARQ Scheme with Adaptive Retransmission (적응 재전송을 적용한 협력 하이브리드 ARQ 기법)

  • Kang, Seong-Kyo;Wang, Jin-Soo;Kim, Yun-Hee;Song, Iick-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.3A
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    • pp.213-220
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    • 2009
  • Cooperative diversity is a promising technique for range extension and diversity increase without the use of multiple transmit antennas at the user equipment. In this paper, we propose a cooperative hybrid automatic repeat request relay method with adaptive retransmission to increase the throughput when the SNR of a source user is low. In the proposed method, the source user transmits the first segment of a codeword to relay users and a base station. If the base station fails to recover the information from the received packet, it requests the source or some relay users to retransmit the packet previously sent. In addition, the retransmission type of a selected user is chosen from repetition or incremental redundancy according to the quality of systematic bits in a turbo codeword. Simulation results show that the proposed method improves the throughput compared to conventional methods, and the improvement is significant when the source user has a low SNR.

An Enhancement of Learning Speed of the Error - Backpropagation Algorithm (오류 역전도 알고리즘의 학습속도 향상기법)

  • Shim, Bum-Sik;Jung, Eui-Yong;Yoon, Chung-Hwa;Kang, Kyung-Sik
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.7
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    • pp.1759-1769
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    • 1997
  • The Error BackPropagation (EBP) algorithm for multi-layered neural networks is widely used in various areas such as associative memory, speech recognition, pattern recognition and robotics, etc. Nevertheless, many researchers have continuously published papers about improvements over the original EBP algorithm. The main reason for this research activity is that EBP is exceeding slow when the number of neurons and the size of training set is large. In this study, we developed new learning speed acceleration methods using variable learning rate, variable momentum rate and variable slope for the sigmoid function. During the learning process, these parameters should be adjusted continuously according to the total error of network, and it has been shown that these methods significantly reduced learning time over the original EBP. In order to show the efficiency of the proposed methods, first we have used binary data which are made by random number generator and showed the vast improvements in terms of epoch. Also, we have applied our methods to the binary-valued Monk's data, 4, 5, 6, 7-bit parity checker and real-valued Iris data which are famous benchmark training sets for machine learning.

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DCGAN-based Compensation for Soft Errors in Face Recognition systems based on a Cross-layer Approach (얼굴인식 시스템의 소프트에러에 대한 DCGSN 기반의 크로스 레이어 보상 방법)

  • Cho, Young-Hwan;Kim, Do-Yun;Lee, Seung-Hyeon;Jeong, Gu-Min
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.14 no.5
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    • pp.430-437
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    • 2021
  • In this paper, we propose a robust face recognition method against soft errors with a deep convolutional generative adversarial network(DCGAN) based compensation method by a cross-layer approach. When soft-errors occur in block data of JPEG files, these blocks can be decoded inappropriately. In previous results, these blocks have been replaced using a mean face, thereby improving recognition ratio to a certain degree. This paper uses a DCGAN-based compensation approach to extend the previous results. When soft errors are detected in an embedded system layer using parity bit checkers, they are compensated in the application layer using compensated block data by a DCGAN-based compensation method. Regarding soft errors and block data loss in facial images, a DCGAN architecture is redesigned to compensate for the block data loss. Simulation results show that the proposed method effectively compensates for performance degradation due to soft errors.

Advanced Multi-Pass Fast Correlation Attack on Stream Ciphers (스트림 암호에 대한 개선된 다중 경로 고속 상관 공격)

  • Kim, Hyun;Sung, Jae-Chul;Lee, Sang-Jin;Park, Hae-Ryong;Chun, Kil-Soo;Hong, Seok-Hie
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.17 no.4
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    • pp.53-60
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    • 2007
  • In a known plaintext scenario, fast correlation attack is very powerful attack on stream ciphers. Most of fast correlation attacks consider the cryptographic problem as the suitable decoding problem. In this paper, we introduce advanced multi-pass fast correlation attack which is based on the fast correlation attack, which uses parity check equation and Fast Walsh Transform, proposed by Chose et al. and the Multi-pass fast correlation attack proposed by Zhang et al. We guess some bits of initial states of the target LFSR with the same method as previously proposed methods, but we can get one more bits at each passes and we will recover the initial states more efficiently.