• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1965-1966
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• 2008

The manipulation of Boolean functions is a fundamental part of computer science, and many problems in the design and testing of digital systems can be expressed as a sequence of operations. It is mainly a paper of our research on the techniques of Boolean function manipulation using Binary Decision Diagram(BDDs) and their applications for VLSI CAD System. In many practical applications related to digital system design, it is a basic technique to use ternary-valued functions. In this paper, we discuss the methods for representing logical values.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.868-873
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• 2008

In this paper, we analyze the burst error performance of LDPC codes on perpendicular magnetic recording(PMR) channel. When burst error is generated on PMR channel, we use channel state information(CSI) to set the LLR information of channel detector zero. We consider the rate 0.94 LDPC codes and use SOVA as channel detector with low complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1176-1178
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• 2016

We propose some binary locally repairable codes with locality 2 uising a parity-check matrix. The minimum distance of the proposed codes is 6. The proposed codes are optimal in the sense of achieving the upper bound of dimension for given length, minimum distance, and locality.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.4
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• pp.335-342
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• 2021

By using HLS when developing a communication system FPGA, HDL code can be automatically generated from a little modified C/C++ source code used for performance verification, which has the advantage of shortening the development period. In this paper, a method of designing a telemetry standard 106-17 LDPC decoder in C language is proposed using Xilinx's Vivado HLS, and by synthesizing Spartan-7 and Kintex-7 as target devices, throughput and FPGA utilization rate was compared.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.10
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• pp.852-857
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• 2013

In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2207-2214
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• 2010

Underwater acoustic(UWA) communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of UWA channel causes signal distortion and error floor. In this paper, we proposed split input bits of channel decoder using method of maximum value, average value, LLR value for optimal estimation. Channel coding method is LDPC(N size=16000) standard in DVB-S2. As shown in simulation results, the performance of LLR value method is better than other methods.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.3-10
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• 2015

Application of polar codes to rate-adaptive asymmetric Slepian-Wolf coding is considered. We propose a method of constructing polar codes which supports rate adaptivity. The proposed polar distributed source coding with successive cancellation list decoding performs closer to the Slepian-Wolf bound than the low density parity check accumulate (LDPCA) codes in the same framework.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.10
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• pp.831-835
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• 2020

By automatically generating HDL codes from C/C++ source codes, HLS makes it possible to shorten FPGA system developing period through easy timing control and structure change. We designed LDPC encoder for telemetry standard 106-17 with Xilinx Vivado HLS and showed hardware structure can be easily adapted for different purposes through minor C code modification. Synthesis results targeting Spartan-7 xc7s100 device are presented for throughput and hardware complexity comparison.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9C
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• pp.683-690
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• 2008

By using inherent stopping criteria of LDPC codes, the average number of iterations can be substantially reduced at high signal to noise ratio (SNR). However, we encounter a problem when hybrid automatic repeat request (H-ARQ) systems are applied. Frequent failures of decoding at low SNR region imply that the decoder leaches the maximum number of iterations frequently and thus the decoding complexity increases. In this paper, we propose a combination of stopping criteria using the syndrome weight of tentative codeword. By numerical analysis, it is shown that the decoding complexity of given H-ARQ system is reduced by 70-80% with the proposed algorithms.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.226-231
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• 2010

This paper proposes a new coding technique for constructing error correcting high rate DC-free multimode code using a generator matrix generated from a sparse parity-check matrix. The scheme exploits high rate generator matrixes for producing distinct candidate codewords. The decoding complexity depends on whether the syndrome of the received codeword is zero or not. If the syndrome is zero, the decoding is simply performed by expurgating the redundant bits of the received codeword. Otherwise, the decoding is performed by a sum-product algorithm. The performance of the proposed scheme can achieve a reasonable DC-suppression and a low bit error rate.