대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

패리티 비트를 확장한 오류 검사에 관한 연구

Error Detection using Advanced Parity Bit

  • 김인수 (성균관대학교 정보통신공학부) ;
  • 민형복 (성균관대학교 정보통신공학부) ;
  • 김용현 (성균관대학교 정보통신공학부) ;
  • 김신택 (대림대학 컴퓨터정보계열)
  • Kim, In-Soo (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Min, Hyoung-Bok (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Yong-Hyun (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Shin-Taek (Division of Computer Science and Information, Daelim College)
  • 발행 : 2008.07.16
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초록

The manipulation of Boolean functions is a fundamental part of computer science, and many problems in the design and testing of digital systems can be expressed as a sequence of operations. It is mainly a paper of our research on the techniques of Boolean function manipulation using Binary Decision Diagram(BDDs) and their applications for VLSI CAD System. In many practical applications related to digital system design, it is a basic technique to use ternary-valued functions. In this paper, we discuss the methods for representing logical values.

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