• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.59-66
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• 1998

In this paper, the high-speed decoder for RS(Reed-Solomon) code, one of the most popular error correcting code, is implemented using VHDL. This RS decoder is designed in transform domain instead of most time domain. Because of the simplicity in structure, transform decoder can be easily realized VLSI chip. Additionally the pipeline architecture, which is similar to a systolic array is applied for all design. Therefore, This transform RS decoder is suitable for high-rate data transfer. After synthesis with FPGA technology, the decoding rate is more 43 Mbytes/s and the area is 1853 LCs(Logic Cells). To compare with other product with pipeline architecture, this result is admirable. Error correcting ability and pipeline performance is certified by computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.79-86
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• 2008

H.264/AVC is the newest international video coding standard developed by the joint ITU-T and ISO/IEC standards organizations. This newest video coding standard offers much higher coding efficiency than the H.261, H.263 and MPEG-4. But it has high computing complexity and high H/W resources wasting problem. This paper described the two unit parallel pipeline structure. This new structure comparing with standard model decreased the computing complexity of 67% and the H/W resources waste of 3%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.99-105
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• 2021

Today, a superscalar processor is the basic unit or an essential component of a multi-core processor, SoCs, and GPUs. Hence, a high-performance out-of-order superscalar processor must be adopted for these systems to maximize its performance. The superscalar processor fetches, issues, executes, and writes back multiple instructions per cycle by utilizing reorder buffers and reservation stations to dynamically schedule instructions in a pipelined scheme. In this paper, a fully pipelined out-of-order superscalar processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, the program composed of ARM instructions is successfully performed.

• Journal of IKEEE
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• v.24 no.4
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• pp.1086-1092
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• 2020

An autonomous agent for real world should be able to recognize text in scenes. With the advancement of deep learning, various DNN models have been utilized for transformation, feature extraction, and predictions. However, the existing state-of-the art STR (Scene Text Recognition) engines do not achieve the performance required for real world applications. In this paper, we introduce a performance-improvement method through an add-on composed of an OCR (Optical Character Recognition) engine and a classifier for STR engines. On instances from IC13 and IC15 datasets which a STR engine failed to recognize, our method recognizes 10.92% of unrecognized characters.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.429-430
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• 2008

FFT(Fast Fourier Transform)는 멀티미디어 통신 및 디지털 신호처리 분야, 특히 무선통신이나 디지털 방송 등에서 쓰이는 OFDM(Orthogonal Frequency Division Multiplexing)에서 필수적인 역할을 하고 있다. 본 논문에서는 파이프라인 FFT 프로세서 설계의 다양한 알고리즘 및 하드웨어 구조에 대해 살펴보고 이를 한 눈에 파악할 수 있는 설계 가이드라인을 제시한다. 또한 분석 중 Radix-2 Single-path Delay Feedback의 복소곱셈기의 비효율적인 면을 찾고 새로운 R2SDF 구조를 제안한다.

• Journal of the Korea Society of Computer and Information
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• v.8 no.4
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• pp.111-116
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• 2003

We proposed a optimal clock period selection algorithm for low power Register Transfer Level design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the proposed algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm. The experiment result is to set the same result AR and HAL filter on the high level benchmark and to reduce in the case of two pipe stage 10.5% and three pipe stage as many as 33.4%.

• Fire Science and Engineering
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• v.22 no.1
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• pp.10-15
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• 2008

In this study, seismic design in sprinkler head pipeline of water extinguishing system has been carried out. This study describes a generation of artificial earthquake wave compatible with seismic design spectrum, and also analyzed the dynamic response spectra by the simulated earthquake motion. This study constructed powerful engineering base for seismic design, and presented seismic design techniques of water and gas extinguishing piping system. Also, this study readied basis that can apply seismic design and performance estimation of fire fighting system and performance rating as well as pipeline of water extinguishing system from result of this research. Hereafter, if additional research by earthquake magnitude and ground kind is approached, reliance elevation, safety raising and performance based design of fire fighting system see to achieve.

• Journal of the Korean Society for Marine Environment & Energy
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• v.19 no.4
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• pp.286-296
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• 2016

Offshore CCS technology is to transport and inject $CO_2$ which is captured from the power plant into the saline aquifer or depleted oil-gas fields. The more accumulated injected $CO_2$, the higher reservoir pressure increases. The increment of reservoir pressure make a dramatic change of the operating conditions of transport and injection systems. Therefore, it is necessary to carefully analyze the effect of operating condition variations over the injection period in early design phase. The objective of this study is to simulate and analyze the $CO_2$ behavior in the transport and injection systems over the injection period. The storage reservoir is assumed to be gas field in the East Sea continental shelf. The whole systems were consisted of subsea pipeline, riser, topside and wellbore. Modeling and numerical analysis were carried out using OLGA 2014.1. During the 10 years injection period, the change of temperature, pressure and phase of $CO_2$ in subsea pipelines, riser, topside and wellbore were carefully analyzed. Finally, some design guidelines about compressor at inlet of subsea pipeline, heat exchanger on topside and wellhead control were proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.231-239
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• 2007

This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.