• 한국정보통신설비학회:학술대회논문집
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• 2004.08a
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• pp.115-118
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• 2004

본 논문에서는 파이프라인 아키텍처 기반의 네트워크 프로세서를 이용한 네트워크 시스템 개발에 대해 다룬다. 파이프라인 아키텍처는 구조상 Hazards 문제가 발생할 수 있으며 이는 시스템의 성능에 중요한 영향을 주게 된다. 또한 네트워크 프로세서는 고수준의 프로그래밍 모델을 제공하므로 고속의 패킷 처리를 위한 코드 작성이 수월하다. 따라서 파이프라인 아키텍처 기반의 네트워크 프로세서를 이용한 시스템 개발시 Hazards 문제를 피할 수 있는 방법과 효율적인 패킷 처리를 위한 코드 작성에 대한 지침을 제시하고 그 방법이 일반적인 방법보다 효율적임을 확인하였다.

• Review of KIISC
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• v.30 no.6
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• pp.83-89
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• 2020

CPU 마이크로아키텍처는 하드웨어 자원을 공유하거나 투기적 실행과 비순차 실행 등 파이프라인 효율을 극대화하는 방법을 통해 성능 최적화를 달성한다. 그러나 보안을 고려하지 않은 설계 구조로 인해 마이크로아키텍처에 심각한 보안 취약점들을 내포하고 있으며 이는 각종 시스템 보호 메커니즘들을 무력화할 수 있는 시스템 공격으로 이어지고 있다. 본 논문에서는 CPU 마이크로아키텍처의 취약점 및 이를 활용한 공격 기술을 소개하고 최근 주요 보안 학술대회에서 발표된 관련 논문들을 중심으로 최신 연구 동향을 살펴본다.

• Journal of KIISE
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• v.42 no.8
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• pp.1010-1021
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• 2015

Big data systems are widely used to collect large-scale log data, so it is very important for these systems to operate with a high level of performance. However, the current Hadoop-based big data system architecture has a problem in that its performance is low as a result of redundant processing. This paper solves this problem by improving the design of the Hadoop system architecture. The proposed architecture uses the batch-based data collection of the existing architecture in combination with a single processing method. A high level of performance can be achieved by analyzing the collected data directly in memory to avoid redundant processing. The proposed architecture guarantees system expandability, which is an advantage of using the Hadoop architecture. This paper confirms that the proposed architecture is approximately 30% to 35% faster in analyzing and processing data than existing architectures and that it is also extendable.

• The Journal of Korean Association of Computer Education
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• v.18 no.2
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• pp.71-81
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• 2015

In the EISC processor, the Instruction Queue (IQ) supporting LERI folding and loop buffering occupies roughly 20% of real estate, and its efficient utilization is a key for performance. This paper presents an architectural enhancement for the IQ utilization with return address stack (RAS) in the EISC processor. The proposed architecture eliminates the RAS corruption from the wrong-path, taking advantage of shallow pipeline. In experiments, a 4-entry RAS reduces the number of IQ flushes by up to 58.90% over baseline, and an 8-entry RAS by up to 61.28%. The experiments show up to 3.47% performance improvement with 8-entry RAS and up to 3.15% performance improvement with 4-entry RAS.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.18-20
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• 2011

최근 컴퓨터 비전의 활용 영역이 증가함에 따라 컴퓨터 비전의 대표적인 라이브러리인 openCV의 사용 또한 증가하는 추세이다. openCV 에는 컴퓨터 비전 알고리즘의 특성상 massive 한 연산을 수행해야 하는 부분이 상당수 존재한다. 본 논문은 이러한 연산량의 부담을 줄임으로써 openCV 의 성능 향상을 위한 아키텍처를 연구한다. openCV 의 massive 한 연산은 라이브러리 함수에 있는 내부 반복문에서 발생하기 때문에, 본 논문은 반복문의 특성을 분석하고 이를 가속할 수 있는 아키텍처가 무엇인지 연구한다. 결론적으로 반복문의 각 iteration 이 독립적일 경우에는 SIMD (Single Instruction Multiple Data)와 SIMT (Single Instruction Multiple Thread)이 적합하며 반복문의 각 iteration 이 의존적일 경우에는 MIMD (Multiple Instruction Multiple Data)를 바탕으로 하는 파이프라인 아키텍처가 적합하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.795-805
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• 2012

This paper proposes an algorithm and a hardware architecture for a broadcast communication which has the worst bottleneck among multiprocessor using distributed memory architectures. In conventional system, The pipelined broadcast algorithm is an algorithm which takes advantage of maximum bandwidth of communication bus. But unnecessary synchronization process are repeated, because the pipelined broadcast sends the data divided into many parts. In this paper, the MPI unit for pipeline chain algorithm based on circuit switching removing the redundancy of synchronization process was designed, the proposed architecture was evaluated by modeling it with systemC. Consequently, the performance of the proposed architecture was highly improved for broadcast communication up to 3.3 times that of systems using conventional pipelined broadcast algorithm, it can almost take advantage of the maximum bandwidth of transmission bus. Then, it was implemented with VerilogHDL, synthesized with TSMC 0.18um library and implemented into a chip. The area of synthesis results occupied 4,700 gates(2 input NAND gate) and utilization of total area is 2.4%. The proposed architecture achieves improvement in total performance of MPSoC occupying relatively small area.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.155-164
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• 2015

This paper describes a design and implementation of CABAC decoder, which would handle HEVC syntax elements in adaptively pipelined-parallel computation manner. Even though CABAC offers the high compression rate, it is limited in decoding performance due to context-based sequential computation, and strong data dependency between context models, as well as decoding procedure bin by bin. In order to enhance the decoding computation of HEVC CABAC, the flag-type syntax elements are adaptively pipelined by precomputing consecutive flag-type ones; and multi-bin syntax elements are decoded by processing bins in parallel up to three. Further, in order to accelerate Binary Arithmetic Decoder by reducing the critical path delay, the update and renormalization of context modeling are precomputed parallel for the cases of LPS as well as MPS, and then the context modeling renewal is selected by the precedent decoding result. It is simulated that the new HEVC CABAC architecture could achieve the max. performance of 1.01 bins/cycle, which is two times faster with respect to the conventional approach. In ASIC design with 65nm library, the CABAC architecture would handle 224 Mbins/sec, which could decode QFHD HEVC video data in real time.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.306-312
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• 2000

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.