• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11A
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• pp.1652-1660
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• 2000

본 논문에서는 DS/CDMA (Direct Sequence/Code Division Multipe Access) 시스템에서 임시 판정 함수로서 연판정 함수와 경판정 함수를 적용한 파이프라인화된 직렬 간섭 제어 구조(PSIC, Pipelined Successive Interference Cancellation)의 성능을 수식적으로 분석하고, 모의 실험을 통하여 검증한다. PSIC 구조는 다단 직렬 간섭 제거 구조(MSIC, Multistage Successive Interference Cancellation)가 가지는 복호지연(decoding delay)의 문제를 해결하기 위해 파이프라인 구조를 MSIC에 적용한 것이다. 제안된PSIC 구조는 하드웨어의 복잡도(hardwar complexity)를 희생하여 비트 오율(BER, Bit Error Rate)의 증가 없이 MSIC에서 발생하는 복호 지연을 줄일 수 있다. 또한 제안된 PSIC 구조에서 연판정 함수와 경판정 함수를 각 간섭 제거 단(Cancellation stage)에서의 임시 판정 함수로 사용하여 얻게 되는 PSIC 구조들의 성능을 비교한다. 분석 및 실험 결과에 의하면 제안되 PSIC 구조에서는 경판정 함수를 사용할때의 성능이 연판정 함수를 사용할때의 성능보다 우수함을 알 수 있었다.

• The Journal of the Korea Contents Association
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• v.9 no.2
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• pp.1-9
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• 2009

In this paper, we propose the efficient processing technique for unavailable data in hardware implementation of motion estimator in H.264/AVC with parallel processing architecture. Motion estimation processing in the hardware is generally based on pipe-lining, some MV data of neighbor blocks are not available, whereas all MV data are valid in software processing where the data are sequentially processed. In this paper, we solve the problem of data being unavailable in MVp computation. To minimize the quality degradation caused by unavailable MVs, in the proposed method, the unavailable MV of a neighboring block is replaced with an integer pel unit MV, an MVp of neighboring blocks, or an MVcol (MV of co-located block). Comparing to the conventional method [7], our method outperformed maximally 0.832dB and 0.179dB for QCIF and CIF, respectively, in terms of BDPSNR.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1518-1526
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• 2004

In this paper, an algorithm using wavelet transform for detecting a cut that is a radical scene transition point, and fade and dissolve that are gradual scene transition points is proposed. The conventional methods using wavelet transform for this purpose is using features in both spatial and frequency domain. But in the proposed algorithm, the color space of an input image is converted to YUV and then luminance component Y is transformed in frequency domain using 2-level lifting. Then, the histogram of only low frequency subband that may contain some spatial domain features is compared with the previous one. Edges obtained from other higher bands can be divided into global, semi-global and local regions and the histogram of each edge region is compared. The experimental results show the performance improvement of about 17% in recall and 18% in precision and also show a good performance in fade and dissolve detection.

• Proceedings of the Korean Society of Disaster Information Conference
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• 2017.11a
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• pp.145-146
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• 2017

최근 세계적으로 많은 지진이 발생하고 있으며 기상이변으로 인한 자연재해로 인해 주요 시설물들의 안전성에 관한 관심이 증가하고 있는 추세이다. 특히 비구조 요소의 경우 구조 요소보다 건설 초기 투자비용이 높아 지진이 발생하였을 때 많은 피해가 발생할 가능성이 있으며 비구조 요소의 파괴는 심각한 2차피해로 발전 될 수 있으므로 내진안전성 평가는 반드시 이루어져야 한다고 볼 수 있다. 따라서 본 연구에서는 압착식 조인트의 접촉을 고려한 수계소화설비 파이프라인의 내진성능 평가를 위한 비선형 유한요소 모델을 구축하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.415-417
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• 2003

본 논문에서는 유한 필드 GF(2$^{m}$ ) 상에서 A$B^2$연산을 수행하는 디지트 시리얼(digit-serial) 시스톨릭 구조를 제안하였다. 제안한 구조는 디지트 크기를 적당히 선택했을 때, 비트-패러럴(bit-parallel) 구조에 비해 적은 하드웨어를 사용하고 비트-시리얼(bit-serial) 구조에 비해 빠르다 또한, 제안한 디지트 시리얼 구조에 파이프라인 기법을 적용하면 그렇지 않은 구조에 비해 m=160, L=2 일 때 공간-시간 복잡도가 10.9% 적다.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Korean Journal of Cognitive Science
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• v.7 no.1
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• pp.75-84
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• 1996

In this paper we emphasize the importance of architectural aspects of designing a handwritten numeral recognition program. and describe two architectural design.First, we describe the modular design of a numeral recognition program, and mention its advantages.In this design, a recognizer is composed of 10 binary subrecognizers each of which is responsible for only one class.Rule-based training and neural-based training are presented.Second, we connect two(or more)recognizers serially which we call pipelining connection.The second recognizer may act as verifier for the patterns recognized by the forst recognizer, or as second chance recognizer for the patterns rejected by the first recognizer.Our experimental results obtained till now show the merits of the proposed architectural designs.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2015.10a
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• pp.15-16
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• 2015

해저파이프라인 및 해저케이블 설치해역이 대수심으로 이동함에 따라 육지와는 다른 열악한 시공 환경에 놓이게 된다. 이때 파이프라인 및 케이블이 매설되는 해저지반 상태와 작업이 이루어지는 해역의 해상조건 등은 작업효율에 영향을 미치기 때문에 효율적인 시공이 필요하다. 본 논문은 구조물 매설에 앞서 해저지반 굴삭 작업을 수행하기 위해 ROV 트렌쳐의 하단에 장착되는 워터젯 굴삭기의 작업효율 및 시공성능 추정에 관한 연구이다. 먼저 전산유체해석을 통해 워터젯 굴삭기의 굴삭효율을 극대화할 수 있는 노즐 수량을 정하였고, 모형실험을 수행하여 굴삭기의 시공성능을 예측할 수 있는 최대 굴삭심도 및 최대 굴삭속도를 파악하였다. 이를 바탕으로 실제 운용중인 워터젯 굴삭장비들과 시공성능을 비교 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.