• Journal of the Computational Structural Engineering Institute of Korea
• /
• v.32 no.1
• /
• pp.17-27
• /
• 2019

In this paper, we study the applicability of Tuned Mass Damper(TMD) to improve seismic performance of piping system under earthquake loading. For this purpose, a mode analysis of the target pipeline is performed, and TMD installation locations are selected as important modes with relatively large mass participation ratio in each direction. In order to design the TMD at selected positions, each corresponding mode is replaced with a SDOF damped model, and accordingly the corresponding pipeline is converted into a 2-DOF system by considering the TMD as a SDOF damped model. Then, optimal design values of the TMD, which can minimize the dynamic amplification factor of the transformed 2-DOF system, are derived through GA optimization method. The proposed TMD design values are applied to the pipeline numerical model to analyze seismic performance with and without TMD installation. As a result of numerical analyses, it is confirmed that the directional acceleration responses, the maximum normal stresses and directional reaction forces of the pipeline system are reduced, quite a lot. The results of this study are expected to be used as basic information with respect to the improvement of the seismic performance of the piping system in the future.

• Journal of IKEEE
• /
• v.13 no.2
• /
• pp.253-259
• /
• 2009

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size, low power. The proposed shader processor is a GP-GPU(General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced 60% less than the sizes of previous processors.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.8 no.3
• /
• pp.460-465
• /
• 2007

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB{\sim}-0.63LSB$ and $0.53LSB{\sim}-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.1
• /
• pp.132-140
• /
• 2011

Ultra-High Definition Television (U-HDTV) is a promising candidate for the next generation television. Since the U-HDTV video signal requires a huge amount of data, parallel implementation of the U-HDTV compression system is highly demanding. In the conventional parallel video codec, a video is divided into sub-sequences and the sub-sequences are independently encoded. In this paper, for efficient parallel processing, we propose a pipelined encoding structure which exploits cross-correlation among the sub-sequences. The experimental results demonstrate that the proposed technique improves the coding efficiency and provides the sub-sequences of the balanced visual quality.

• Journal of IKEEE
• /
• v.5 no.1 s.8
• /
• pp.24-34
• /
• 2001

IP address lookup is a major bottleneck of IP packet processing in high speed router. Existing IP lookup methods are focused only on lookup throughput without considering lookup table update. So their slow update can lead to lookup blocking or wrong routing decision based on obsolete routes. Especially existing IP lookup methods based on CAM(content addressable memory) have slow update of O(n) cycles in spite of their high throughput and low area complexity In this paper we proposes a new IP address lookup method based on pipelined CAM architecture(PICAM) with fast update of O(1) cycle of lookup table and high throughput and low area complexity.

• Journal of Korea Society of Industrial Information Systems
• /
• v.4 no.2
• /
• pp.44-50
• /
• 1999

This paper presents a set of techniques to automatically find rate optimal or near rate optimal implementation of shift-invariant flow graphs on pipelined processor, in which pipeline processor has multiple accumulators and internal datapaths. In such case, the problem to be addressed is the scheduling of multiple instruction streams which control all of the pipeline stages. The goal of an automatic scheduler in this context is to rearrange the order of instructions such that they are executed with minimum iteration period between successive iteration of defining flow graphs. The scheduling algorithm described in this paper also focuses on the problem of removing the hazards due to inter-instruction dependencies.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.3
• /
• pp.547-554
• /
• 2008

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.12
• /
• pp.2675-2680
• /
• 2010

Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.12
• /
• pp.730-736
• /
• 2019

The demand for natural gas, which is considered an environmentally friendly energy source, is increasing, and at the same time, the market share of large pipelines for natural gas supply is increasing continuously. On the other hand, the corrosion of such large pipelines reduces the efficiency of natural gas transportation. Therefore, this study aims to establish a strategy for securing the patent rights of related technologies through quantitative analysis of patents on energy-independent high-efficiency corrosion prevention technology for large-scale pipelines for natural gas supply. In this patent technology trend study, Korean, US, Japanese, and European patents filed, published, and registered by June 2018 were analyzed, and a technical classification system and classification criteria were prepared through expert discussion. To use fuel cells as an external power source to prevent the corrosion of natural gas large-scale pipelines, it is believed that rights can be claimed using an energy control system and methods having 1) branch structures of pipeline and facility designs (decompressor/compressor/heat exchanger) and 2) decompression/preheating and pressurization/cooling technology of high pressure natural gas.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2001.04a
• /
• pp.271-274
• /
• 2001

바이패싱 회로는 명령어의 파이프라인의 실행 단계가 종료되자마자 연산 결과를 다음 번 파이프라인 단계의 실행 단계의 실행 유니트에서 사용할 수 있어 명령어 실행 시간이 단축된다. 그러나 바이패싱 회로의 복잡도는 연산처리기가 늘어남에 따라 크게 증가하는 단점이 있으므로 명령어 중복 할당 기법을 적용하면 여러 개의 연산처리기에서 동일한 연산을 수행하여 VLIW 구조에서 가상의 바이패싱 회로가 존재하는 것과 같은 효과를 얻을 수 있다.