• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.193-194
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• 2018

본 논문은 $6kW/L(98W/in^3)$의 전력밀도를 갖는 xEV LDC를 위한 절연형 DC-DC컨버터의 설계 방법을 제안한다. 부피를 가장 많이 차지하는 수동소자의 부피를 줄이기 위해 GaN소자를 적용하여 스위칭 주파수를 700kHz를 적용하였다. 또한 자속 상쇄 개념이 적용된 매트릭스 평면 변압기를 적용하여 변압기의 부피를 크게 줄일 수 있었다. 본 논문에서는 후보 토폴로지들의 비교를 통해 고 전력 밀도에 가장 적합한 토폴로지를 선정하였으며, 자속상쇄 개념 기반의 매트릭스 평면 변압기를 설계방법을 제안하였다.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.998-999
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• 2015

전동열차에서 생성된 회생에너지를 에너지저장장치(Energy Storage System)에 바로 저장하기에는 문제점이 있다. 따라서 본 논문에서는 Super Capacitor를 적용한 컨버터설계 및 시뮬레이션을 하였다. 분석 결과 각 토폴로지의 문제점으로 인해 Super Capacitor의 제거와 배터리의 용량을 증가하여야 한다는 결론을 얻었다.

• Journal of the military operations research society of Korea
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• v.12 no.1
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• pp.71-77
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• 1986

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.348-349
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• 2019

본 논문은 전기자동차용 8.1kW/L의 높은 전력밀도를 갖는 저전압 DC-DC 컨버터(Low-voltage DC-DC converter, LDC)의 설계 방법을 제안한다. 넓은 전압범위에서 높은 전력밀도를 성취하기 위해 위상천이 풀-브릿지(Phase Shift Full-Bridge, PSFB) 컨버터의 2차측 토폴로지 후보군의 비교를 통해 전류-더블러 토폴로지로 토폴로지가 선정되었다. 또한 자속 상쇄 기법이 적용된 매트릭스 변압기를 적용한 PSFB 컨버터와 냉각기의 구조설계를 통해 8.1kW/L의 전력밀도를 달성하였으며 1.8kW 시작품을 제작하여 성능을 검증하였다.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.123-124
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• 2016

본 논문에서는 단상 BESS(Battery Energy Storage System)용 컨버터/인버터 일체형 전력변환시스템을 제안한다. 양방향전력흐름 제어와 경량화를 위한 일체형 전력변환시스템으로 직류 출력 및 교류 출력이 가능한 일체형 토폴로지를 제안한다. 또한 제안 토폴로지에 대해, 배터리 충전 및 배터리에서 부하로 전력 공급을 위한 제안 토폴로지의 제어 알고리즘을 설계하고 이에 대한 유효성을 시뮬레이션 및 실험을 통해 검증한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.1-7
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• 2004

A regular logical topology requires little processing time for routing purposes which may be a desirable property for high-speed networks. Asymmetric bilayered ShuffleNet, proposed by us as a logical topology, can be used to a wavelength division multiplexing ring network to increase the network capacity compared to ShuffleNet. In this paper, asymmetric bilayered ShuffleNet is imbedded on a wavelength division multiplexing ring with the objective of minimizing the total number of wavelengths assigned.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.151-152
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• 2012

본 논문은 전기자동차의 탑재형 충전기 (OBC, On-Board Charger)에 적용 가능한 고효율 역률개선회로 (PFC, Power Factor Correction Circuit)들의 손실을 분석한다. 평균전류모드제어를 이용하여 conventional boost PFC, interleaved boost PFC, semi-bridgeless PFC, totem pole PFC, seudo totem pole PFC, back-to-back bridgeless PFC, interleaved bridgeless PFC 등 7개의 토폴로지를 3.3kW OBC 기반으로 설계하고, 각 토폴로지의 손실을 수식과 PSIM의 thermal module을 이용하여 분석한다. 분석한 결과를 토대로 제시한 토폴로지들의 효율 및 성능을 비교한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.6
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• pp.510-516
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• 2007

The proposed method offers an improved control method for high power density AC/DC adapter by using more energy efficient electrical equipments. Power factor correction (PFC) topology is based on boost topology with boundary conduction mode (BCM). DC/DC topology is based on half-bridge topology with fixed 50% duty and newly introduced off-time control method, which helps to reduce size of the semiconductor and the magnetic devices. Test results with 85W AC/DC adapter (18.5V/4.6A) design show that the measured efficiency is 90% with power density of $36W/in^3$. It also shows low no load power consumption of about 0.5W.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• Journal of Korea Multimedia Society
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• v.12 no.9
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• pp.1297-1308
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• 2009

The life time of a wireless sensor network composed of numerous sensor nodes depend on ones of its sensor nodes. The energy efficiency operation of nodes, therefore, is one of the crucial factors to design the network. Researches based on the hierarchical network topology have been proposed and evolved in terms of energy efficiency. However, in existing researches, application layer data obtained from sensor nodes are not considered properly to compose cluster, including issue that nodes communicate with their cluster heads in TDMA scheduling. In this paper, we suggest an energy-efficient topology control scheme based on application layer data in wireless sensor networks. By using application layer data, sensor nodes form a section which is defined as the area of adjacent nodes that retain similar characteristics of application environments. These sections are further organized into clusters. We suggest an algorithm for selecting a cluster head as well as a way of scheduling to reduce the number of unnecessary transmissions from each node to its cluster head, which based on the degree and the duration of similarity between the node's data and its head's data in each cluster without seriously damaging the integrity of application data. The results show that the suggested scheme can save the energy of nodes and increase the life time of the entire network.