• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.57-64
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• 2019

In this paper, an efficient prediction-based parallel simulation method using spatially partial simulation strategy is proposed for improving both the performance of the event-driven gate-level timing simulation and the debugging efficiency. The proposed method quickly generates the prediction data on-the-fly, but still accurately for the input values and output values of parallel event-driven local simulations by applying the strategy to the simulation at the higher abstraction level. For those six designs which had used for the performance evaluation of the proposed strategy, our method had shown about 3.7x improvement over the most general sequential event-driven gate-level timing simulation, 9.7x improvement over the commercial multi-core based parallel event-driven gate-level timing simulation, and 2.7x improvement over the best of previous prediction-based parallel simulation results, on average.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• The Journal of Korean Academy of Sensory Integration
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• v.16 no.2
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• pp.15-25
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• 2018

Objective : The purpose of this study was to examine the differences between motor functions and executive functions according to the timing of children with attention deficit hyperactivity disorder (ADHD). Methods : The subjects were 32 children with ADHD aged between 6 and 12 living Busan. To assess the timing, Long Form Assessment (LFA) of Interactive Metronome (IM) was used. Bruininks-Oseretsky of Motor Proficiency, Second Edition (BOT-2) were also used to assess motor functions. STROOP Color and Word Test and Children's Color Trails Test were used to evaluate executive functions. Mann-Whitney U tests were used to determine the differences between the executive functions and the motor functions according to the timing. Results : Comparing the inter-group motor functions according to the timing, there was a statistically significant difference in the Fine manual control and Fine motor precision in BOT-2 (p<.05). Comparing the inter-group executive functions according to the timing, there was not statistically significant difference (p>.05). Conclusion : Among the deficits in ADHD children, we could see the differences between motor function and executive function according to timing function. This study would be meaningful in that the results could be a basic data for study on the timing of children of ADHD in the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.31-38
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• 2012

In this paper, a low area timing synchronization structure for the IEEE 802.11a OFDM MODEM SoC is proposed. The timing synchronization block of the IEEE 802.11a OFDM MODEM SoC requires large implementation area. In the proposed timing synchronization structure, it is shown that the number of multiplication can be reduced by using the transposed direct form filter. Furthermore, implementation area of the proposed structure can be more reduced using CSD(Canonic Signed Digit) and Common Sub-expression Sharing techniques. Through Verilog-HDL coding and synthesis, it is shown that the 22.7 % of implementation area can be reduced compared with the conventional one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2310-2316
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• 2010

This paper presents an application of retiming to model checking, a branch of formal verification. Retiming can change the transition relation of a circuit without changing its input-output behaviour by relocating its registers. With the retiming, a given circuit can have a different structure more adequate for model checking. This paper proposes a cost function to reflect the number of registers and the characteristic of its transition relation and develops a heuristic annealing algorithm to search efficiently the circuit structures obtained by retiming. Experimental results show that the proposed method can improve the model checking performance.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1042-1046
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• 2011

In this paper, we analyze the STO (Symbol Timing Offset) problem in conventional ZP-OFDM (Zero Padding-Orthogonal Frequency Division Multiplexing) systems and propose a robust ZP-OFDM system with bi-directional overlap-add scheme to overcome the problem. The proposed ZP-OFDM system is able to preserve the orthogonality between subcarriers and reduce the interference from other ZP-OFDM symbols due to the BOA scheme, which exploits both ZP intervals of the previous and the current ZP-OFDM symbols, even though serious STOs result from inaccurate symbol timing synchronization. Simulation results verify that the proposed ZP-OFDM system is superior to the conventional ZP-OFDM system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.383-388
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• 1998

본 논문에서는 LMDS(Local Multipoint Distributed Services) 시스템의 역방향 채널에서 TDMA(Time Division Multiple Access) 방식으로 ATM(Asynchronous Transfer Mode) 셀을 효율적으로 전송하기 위해 전치부호를 줄일 수 있는 블록복조 알고리즘을 적용한 $\pi$/4 QPSK 변복조 방식 시스템을 제안하고, 블록복조의 동기성능을 향상시키기 위해 새로운 반송파 동기회로를 설계하였다. 제안한 블록동기복조 알고리즘을 적용한 $\pi$/4 QPSK 변복조 방식 시스템은 LMDS 환경에서 ATM 셀 단위의 버스트 데이터로 반송파 위상동기, 심벌 타이밍 동기, 슬롯 타이밍 동기 둥을 수행할 때 전치부호를 아주 적게 사용하므로 효율적인 프레임 전송을 얻어질 수 있도록 하고 있다. 제안한 방식의 성능평가를 위한 모의실험은 LMDS 채널환경과 프레임 구조의 버스트 모드 전송환경에서 심벌 타이밍 동기, 주파수 오프셋, 반송파 위상동기, 페이딩 채널에 따라 수행하였다. 본 논문에서 제안한 블록동기복조 알고리즘을 적용한 $\pi$/40 QPSK 변복조 방식 시스템을 모의수행을 통하여 분석한 결과, 페이딩 환경에서 심벌 타이밍 동기, 주파수 오프셋, 반송파 위상동기할 때 전치부호를 아주 적게까지 줄이더라도 좋은 성능을 발휘함을 확인할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.659-665
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• 2008

If ranging processes are not frequent in an uplink OFDMA system, the timing synchronization between base and mobile stations may not be maintained. Especially in the case of infrequent random accesses in a large cell, timing offsets can be considerable and the destroyed orthogonality of OFDMA signals may result in the degraded performance. This paper proposes a novel random access scheme for uplink OFDMA systems, which support the orthogonality of OFDMA signals with timing offsets by allowing a random access OFDMA symbol shorter than a normal one. In order to make uplink OFDMA systems robust to timing offsets, the proposed scheme inserts a zero-padding region in an OFDMA symbol.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.522-530
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• 2009

In this paper, we propose an efficient methodology to fix timing violation in ECO step for ASIC process. Timing violation can occur from various reasons and the major cause is inconsistent correlation between EDA tools. The most frequent violation is setup time and hold time violation. First, we analyzed the reason of violation creation, and then proposed the adjusting method for overcome them. Each violation can be fixed by increasing data required time or decreasing data arrival time. We proposed the detailed technique on a case basis. It is difficult to execute these methods by routine of algorithm or principle. Therefore ASIC engineer needs to apply these technique to violation as conditions of the implemented design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.771-778
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• 2002

We investigate the design of an interpolation filter of a MF-TDMA demodulator which is applied to DVB-RCS. If sampling is not synchronized to the data symbols, timing adjustment in digital receiver must be performed by interpolation. It is impossible that conventional sinc interpolation filter coefficients are actually extended to infinity. We propose a Kaiser window interpolation filter and a sinc interpolation filter using th Kaiser window. Simulation results show that the performance improvement is realized by employing the proposed interpolation filter.