• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.163-166
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• 2002

무선 인터넷 사용의 증가와 함께 PDA 또는 무선단말기와 같은 제한된 시스템 환경에 적합한 보안 서비스의 필요성이 증가되고 있다. 무선환경을 위해 제공되어야 할 다양한 보안 서비스 중 인증 및 키 합의를 위한 과정은 보안상 매우 민감한 부분이다. 안전한 프로토콜 설계에서 통신에 참여하는 개체들에 대한 인증 및 이후 진행되는 해당 세션의 안전성 확보를 위한 세션키 설정, 서비스 사용자에 대한 익명성 보장 등이 고려되어야 한다. 본 논문에서는 무선 인터넷의 한정된 시스템 환경을 고려한 타원 곡선 암호시스템(ECC) 기반의 인증 및 키 합의 프로토콜을 제안한다.

• Journal of KIISE:Information Networking
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• v.29 no.4
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• pp.333-345
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• 2002

As computers and networks become popular, distributing information on the Internet is common in our daily life. Also, the explosion of the Internet, of wireless digital communication and data exchange on Internet has rapidly changed the way we connect with other people. But secure mail is gaining popularity abroad and domestically because of their nature of providing security. That is. It has been used a variety of fields such as general mail and e-mail for advertisement. But, As the data transmitted on network can be easily opened or forged with simple operations. Most of existing e-mail system don't have any security on the transmitted information. Thus, security mail system need to provide security including message encryption, content integrity, message origin authentication, and non-repudiation. In this paper, we design and implement secure mail system with secure key agreement algorithm, non-repudiation service, and encryption capability to provide services for certification of delivery and certification of content as well as the basic security services.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.37-44
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• 2001

In this paper, an efficient architecture for the ECC multiplier in GF(2") is proposed. We give a design example for the irreducible trinomials $x_{193}\;+\;x_{15}\;+\;1$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. A digit-serial multiplier with a digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The elliptic curve used in this implementation is defined by Weierstrass equations. The measured results show that the proposed multiplier it 0.3 times smaller than the bit-serial LFSR multiplier.lier.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2002.11a
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• pp.306-310
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• 2002

이동 통신의 급격한 발달로 다양한 부가가치서비스가 등장하고, 이러한 서비스를 좀더 편리하고 안전하게 사용하고 싶어하는 사용자와 부가가치서비스를 제공하는 VASP(Value -Added Service Provider) 사이의 보안이 필수적인 것이 되었다. 이를 위하여 이동 통신 환경의 한계인 제한된 자원과 제한된 계산력을 극복할 수 있도록 적은키 길이를 가지고 보다 안전한 서비스를 제공할 수 있는 타원곡선 암호시스템(ECC)를 기반으로 하여 부가가치서비스에 효율적인 인증 및 키 합의 프로토콜을 제안하고, 차세대 이동통신시스템에 적용해본다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.394-402
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• 2010

At a recent, enterprises based on online-service are established because of rapid growth of information network. These enterprises collect personal information and do customer management. If customers use a paid service, company send billing information to customer and customer pay it. Such circulation and management of information is big issue but most companies don't care of information security. Actually, personal information that was managed by largest internal open-market was exposed. For safe customer information management, this paper proposes the method that decrease load of RSA cryptography algorithm that is commonly used for preventing from illegal attack or hacking. The method for decreasing load was designed by Binary NAF Method and it can operates modular Exponentiation rapidly. We implemented modular Exponentiation algorithm using existing Binary Method and Windows Method and compared and evaluated it.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.6
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• pp.3-12
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• 2011

A hashing function that maps arbitrary messages directly onto curve points (MapToPoint) has non-negligible complexity in pairing-based cryptosystems. Unlike elliptic curve cryptosystems, pairing-based cryptosystems require the hashing function in ternary fields. Barreto et al. observed that it is more advantageous to hash the message to an ordinate instead of an abscissa. So, they significantly improved the hashing function by using a matrix with coefficients of the abscissa. In this paper, we improve the method of Barreto et al. by reducing the matrix. Our method requires only 44% memory of the previous result. Moreover we can hash a message onto a curve point 2~3 times faster than Barreto's Method.

• The KIPS Transactions:PartC
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• v.11C no.5
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• pp.569-576
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• 2004

Conventional researches of standard tool validating public key cryptographic algorithm have been studied for the internet environment, not for the mobile internet. It is important to develop the validation tool for establishment of interoperability and convenience of users in mobile internet. Therefore, this paper presents the validation tool of Elliptic Curie Cryptography algorithm that can test if following X9.62 technology standard specification. The validation tool can be applied all information securities using ECDSA, ECKCDSA, ECDH, etc. Moreover, we can en-hace the precision of validation through several experiments and perform the validation tool in the online environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.656-658
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• 2013

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of an elliptic curve crypto-engine server farm. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.